公开(公告)号：US20180190569A1

公开(公告)日：2018-07-05

申请号：US15855752

申请日：2017-12-27

Applicant: Huawei Technologies Co., Ltd.

Inventor： HuiLi Fu ,  Shujie Cai ,  Xiao Hu

IPC: H01L23/373 ,  H01L23/538 ,  H01L23/00 ,  H01L21/48

CPC classification number: H01L23/3735 ,  H01L21/4853 ,  H01L21/4871 ,  H01L23/3135 ,  H01L23/373 ,  H01L23/538 ,  H01L24/16 ,  H01L24/48 ,  H01L25/0655 ,  H01L25/50 ,  H01L2224/16225 ,  H01L2224/48225 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19105 ,  H01L2924/00012 ,  H01L2224/45099

Abstract: A chip package structure, including a substrate, multiple chips and multiple discrete devices that are packaged on an upper surface of the substrate, and a heat dissipation apparatus, where the heat dissipation apparatus includes an insulation layer and a thermally conductive layer that are laminated. The insulation layer completely encloses and adheres to outer surfaces of the multiple chips, outer surfaces of the multiple discrete devices, and the upper surface of the substrate and configured to conduct heat generated by the multiple chips and the multiple discrete devices to the thermally conductive layer and the substrate such that the heat generated by the multiple chips and the multiple discrete devices dissipated using the thermally conductive layer and the substrate.

公开(公告)号：US10903135B2

公开(公告)日：2021-01-26

申请号：US15855752

申请日：2017-12-27

Applicant: Huawei Technologies Co., Ltd.

Inventor： HuiLi Fu ,  Shujie Cai ,  Xiao Hu

IPC: H01L23/373 ,  H01L25/00 ,  H01L25/065 ,  H01L23/31 ,  H01L21/48 ,  H01L23/538 ,  H01L23/00

Abstract: A chip package structure, including a substrate, multiple chips and multiple discrete devices that are packaged on an upper surface of the substrate, and a heat dissipation apparatus, where the heat dissipation apparatus includes an insulation layer and a thermally conductive layer that are laminated. The insulation layer completely encloses and adheres to outer surfaces of the multiple chips, outer surfaces of the multiple discrete devices, and the upper surface of the substrate and configured to conduct heat generated by the multiple chips and the multiple discrete devices to the thermally conductive layer and the substrate such that the heat generated by the multiple chips and the multiple discrete devices dissipated using the thermally conductive layer and the substrate.