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    Encoding Method and Device, and Apparatus
    2.
    发明申请
    Encoding Method and Device, and Apparatus 审中-公开

    公开(公告)号：US20190165813A1

    公开(公告)日：2019-05-30

    申请号：US16261220

    申请日：2019-01-29

    Applicant: HUAWEI TECHNOLOGIES CO., LTD.

    Inventor： Xiaocheng LIU ,  Ying CHEN ,  Rong LI

    IPC: H03M13/13 ,  H03M13/00 ,  H04L1/00

    Abstract: The present disclosure relates to encoding method and devices. One example method includes determining N to-be-encoded bits, where the N to-be-encoded bits include information bits and frozen bits, obtaining a first polarization weight vector including polarization weights of N polarized channels, where the N to-be-encoded bits correspond to the N polarized channels, determining positions of the information bits based on the first polarization weight vector, and performing polar encoding on the N to-be-encoded bits to obtain polar-encoded bits.

    SIGNAL PROCESSING METHOD AND APPARATUS THEREOF
    5.
    发明公开
    SIGNAL PROCESSING METHOD AND APPARATUS THEREOF 审中-公开

    公开(公告)号：US20240030931A1

    公开(公告)日：2024-01-25

    申请号：US18477105

    申请日：2023-09-28

    Applicant: HUAWEI TECHNOLOGIES CO., LTD.

    Inventor： Tianhang YU ,  Xiaocheng LIU ,  Gongzheng ZHANG ,  Shengchen DAI ,  Rong LI ,  Jun WANG

    IPC: H03M1/08

    CPC classification number: H03M1/0854 ,  H03M1/0836

    Abstract: A signal processing method and an apparatus thereof. A first signal is received, wherein the first signal includes x symbols. N types of quantization levels are determined based on a signal distribution parameter of the first signal. A second signal is determined based on the first signal. Quantization processing is performed on the second signal to obtain x groups of first quantization results, wherein the x symbols are in one-to-one correspondence with the x groups of first quantization results. The x groups of first quantization results are mapped to a quantized first signal, wherein the quantized first signal includes x quantization levels, and each group of first quantization results is mapped to one of the N types of quantization levels. Signal processing is performed on the quantized first signal.

    CODING METHOD AND APPARATUS, AND DEVICE
    6.
    发明申请
    CODING METHOD AND APPARATUS, AND DEVICE 审中-公开

    公开(公告)号：US20200059246A1

    公开(公告)日：2020-02-20

    申请号：US16661931

    申请日：2019-10-23

    Applicant: HUAWEI TECHNOLOGIES CO., LTD.

    Inventor： Ying CHEN ,  Xiaocheng LIU ,  Lingchen HUANG ,  Yue ZHOU ,  Rong LI ,  Hejia LUO ,  Jun WANG

    IPC: H03M13/13 ,  H03M13/00

    Abstract: A polar code coding/decoding method, a sending device, and a receiving device are disclosed. The method includes: selecting, by a sending device, K non-punctured-position sequence numbers as a reference sequence number set based on a quantity K of information bits and a reliability-based order of N polarized channels of a polar code whose code length is N, where a reliability of a polarized channel corresponding to any sequence number in the reference sequence number set is greater than or equal to reliabilities of polarized channels corresponding to remaining (N−K) sequence numbers; determining, by the sending device, an information-bit sequence number set based on a determining condition and the reference sequence number set; and performing, by the sending device, polar coding on to-be-coded bits based on the information-bit sequence number set.

    POLAR CODING METHOD, APPARATUS, AND DEVICE
    7.
    发明申请
    POLAR CODING METHOD, APPARATUS, AND DEVICE 有权

    公开(公告)号：US20210176007A1

    公开(公告)日：2021-06-10

    申请号：US17132566

    申请日：2020-12-23

    Applicant: HUAWEI TECHNOLOGIES CO., LTD.

    Inventor： Rong LI ,  Gongzheng ZHANG ,  Ying CHEN ,  Xiaocheng LIU ,  Jun WANG

    IPC: H04L1/00 ,  H03M13/00 ,  H03M13/13

    Abstract: Embodiments of this application disclose a polar coding method, apparatus, and device, so as to reduce storage overheads of a system. A sequence for polar coding is obtained based on a length M of a target polar code, wherein the sequence comprises L sequence numbers, ordering of the L sequence numbers in the sequence is the same as ordering of the L sequence numbers in a maximum mother code sequence, wherein the maximum mother code sequence is obtained by sorting N sequence numbers of N polarized channels in ascending order or descending order of reliability metrics, wherein L and N are integer power of 2, M is smaller than or equal to L, L is smaller than or equal to N.

    DECODING METHOD AND APPARATUS
    8.
    发明申请
    DECODING METHOD AND APPARATUS 审中-公开

    公开(公告)号：US20200343916A1

    公开(公告)日：2020-10-29

    申请号：US16923898

    申请日：2020-07-08

    Applicant: Huawei Technologies Co., Ltd.

    Inventor： Jiajie TONG ,  Huazi ZHANG ,  Yunfei QIAO ,  Rong LI ,  Xiaocheng LIU ,  Jun WANG

    IPC: H03M13/45 ,  H03M13/09

    Abstract: A decoding method and apparatus are provided, to improve a degree of parallelism in decoded bit decisions and reduce a decoding delay. The method includes: performing a hard decision on each LLR in an inputted LLR vector having a length of M to obtain a first vector, where M≤N and N is a length of to-be-decoded information; sequentially performing negation of some elements of the first vector to obtain L vectors; and then determining decoding results of the LLR vector based on the L vectors.

    TEST APPARATUS AND TESTABLE ASYNCHRONOUS CIRCUIT
    10.
    发明申请
    TEST APPARATUS AND TESTABLE ASYNCHRONOUS CIRCUIT 审中-公开

    公开(公告)号：US20170160340A1

    公开(公告)日：2017-06-08

    申请号：US15432741

    申请日：2017-02-14

    Applicant: Huawei Technologies Co., Ltd.

    Inventor： Zhen XU ,  Yuqing ZHAO ,  Xiaocheng LIU

    IPC: G01R31/28 ,  G01R31/317 ,  G06F11/25

    CPC classification number: G01R31/2882 ,  G01R31/31704 ,  G01R31/318541 ,  G06F11/25

    Abstract: Disclosed are a test apparatus and a testable asynchronous circuit. The test apparatus includes: a first input end, a second input end, a third input end, a fourth input end, a fifth input end, a first selector, a second selector, a D flip-flop, and a first output end. The first input end is configured to input a data signal or a test result of a previous circuit under test; the second input end is configured to input a test excitation signal or a test result that is output by a previous test apparatus; the third input end is configured to input a clock signal; the fourth input end is configured to input a selection signal; and the fifth input end is configured to input a selection signal.

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