Gm-APD array lidar imaging method and system under strong background noise

    公开(公告)号:US11474251B2

    公开(公告)日:2022-10-18

    申请号:US16898404

    申请日:2020-06-10

    Abstract: The disclosure discloses a Gm-APD array lidar imaging method under strong background noise, comprising following steps: respectively acquiring two sets of cumulative detection data of the Gm-APD array lidar at two different opening times of a range gate of the Gm-APD array lidar under strong background noise; respectively performing a statistic operation on the two sets of cumulative detection data of the Gm-APD array lidar with respect to all pixels, to obtain two cumulative detection result histograms of the Gm-APD array lidar; determining a range interval of the imaging target according to the two cumulative detection result histograms; and acquiring a lidar image by a peak discrimination method in the range interval of the imaging target. The Gm-APD array lidar imaging method according to the present disclosure is capable of improving the laser image quality by eliminating the interference of strong background noise in other range intervals.

    GM-APD ARRAY LIDAR IMAGING METHOD AND SYSTEM UNDER STRONG BACKGROUND NOISE

    公开(公告)号:US20210041568A1

    公开(公告)日:2021-02-11

    申请号:US16898404

    申请日:2020-06-10

    Abstract: The disclosure discloses a Gm-APD array lidar imaging method under strong background noise, comprising following steps: respectively acquiring two sets of cumulative detection data of the Gm-APD array lidar at two different opening times of a range gate of the Gm-APD array lidar under strong background noise; respectively performing a statistic operation on the two sets of cumulative detection data of the Gm-APD array lidar with respect to all pixels, to obtain two cumulative detection result histograms of the Gm-APD array lidar; determining a range interval of the imaging target according to the two cumulative detection result histograms; and acquiring a lidar image by a peak discrimination method in the range interval of the imaging target. The Gm-APD an-ay lidar imaging method according to the present disclosure is capable of improving the laser image quality by eliminating the interference of strong background noise in other range intervals.

    Radiation-hardened storage unit
    3.
    发明授权
    Radiation-hardened storage unit 有权
    辐射硬化存储单元

    公开(公告)号:US08988922B1

    公开(公告)日:2015-03-24

    申请号:US14142987

    申请日:2013-12-30

    CPC classification number: G11C11/4125

    Abstract: A radiation-hardened storage unit, including a basic storage unit, a redundant storage unit, and a two-way feedback unit. The basic storage unit includes a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, and a fourth PMOS transistor. The first PMOS transistor and the second PMOS transistor are read-out access transistors. The third PMOS transistor and the fourth PMOS transistor are write-in access transistors. The redundant storage unit includes a fifth PMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, and an eighth PMOS transistor. The fifth PMOS transistor and the sixth PMOS transistor are read-out access transistors. The seventh PMOS transistor and the eighth PMOS transistor are write-in access transistors. The two-way feedback unit is configured to form a feedback path between the storage node and the redundant storage node.

    Abstract translation: 辐射硬化存储单元,包括基本存储单元,冗余存储单元和双向反馈单元。 基本存储单元包括第一PMOS晶体管,第二PMOS晶体管,第三PMOS晶体管和第四PMOS晶体管。 第一PMOS晶体管和第二PMOS晶体管是读出存取晶体管。 第三PMOS晶体管和第四PMOS晶体管是写入存取晶体管。 冗余存储单元包括第五PMOS晶体管,第六PMOS晶体管,第七PMOS晶体管和第八PMOS晶体管。 第五PMOS晶体管和第六PMOS晶体管是读出存取晶体管。 第七PMOS晶体管和第八PMOS晶体管是写入存取晶体管。 双向反馈单元被配置为在存储节点和冗余存储节点之间形成反馈路径。

    Method for generating row transposed architecture based on two-dimensional FFT processor

    公开(公告)号:US09965386B2

    公开(公告)日:2018-05-08

    申请号:US15233601

    申请日:2016-08-10

    CPC classification number: G06F12/06 G06F12/0207 G06F17/142 G06F2212/1016

    Abstract: The invention discloses a method for generating a row transposed architecture based on a two-dimensional FFT processor, comprising the following characteristic: the FFT processor includes an on-chip row transposition memory for storing an image row transposition result. When the size of the row transposition result exceeds the capacity of the on-chip memory, the first 2k data of a row of the two-dimensional array after row transformation is written into the on-chip row transposition memory, the remaining data is written into the off-chip SDRAM, and k is acquired through calculation according to the row transposition result and the capacity of the on-chip row transposition memory. The on-chip memory is divided into two memories A and B used for storing the row transposition partial result and temporarily storing data read from off-chip SDRAM. When data is read from the memory A or B column by column for FFT column transposition, SDRAM is accessed in a row burst manner and data is written into the empty memory A or B alternately, and finally SDRAM is empty through repetitive ping-pong switching between the memories A and B. The row transposed architecture is capable of substantially reducing cross-line accessing frequency of SDRAM and improving two-dimensional FFT execution speed.

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