公开(公告)号：US20120193798A1

公开(公告)日：2012-08-02

申请号：US13129321

申请日：2011-02-26

申请人： Huicai Zhong ,  Qingqing Liang ,  Zhijiong Luo ,  Huilong Zhu

发明人： Huicai Zhong ,  Qingqing Liang ,  Zhijiong Luo ,  Huilong Zhu

IPC分类号： H01L23/48 ,  H01L23/482 ,  H01L21/768

CPC分类号： H01L23/53276 ,  H01L21/76807 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/76847 ,  H01L21/76877 ,  H01L2221/1094 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention relates to a semiconductor device structure and a method for manufacturing the same; the structure comprises: a semiconductor substrate on which a device structure is formed thereon; an interlayer dielectric layer formed on the device structure, wherein a trench is formed in the interlayer dielectric layer, the trench comprises an incorporated via trench and a conductive wiring trench, and the conductive wiring trench is positioned on the via trench; and a conductive layer filled in the trench, wherein the conductive layer is electrically connected with the device structure; wherein the conductive layer comprises a conductive material and a nanotube/wire layer surrounded by the conductive material. Wherein, the conductive layer comprises a conductive material and a nanotube/wire layer surrounded by the conductive material. The conductive layer of the structure has better thermal conductivity, conductivity and high anti-electromigration capability, thus is able to effectively prevent metal ions from diffusing outwards.

摘要翻译： 半导体器件结构及其制造方法技术领域本发明涉及半导体器件结构及其制造方法。 该结构包括：其上形成有器件结构的半导体衬底; 在所述器件结构上形成的层间电介质层，其中在所述层间介质层中形成沟槽，所述沟槽包括并入的通孔沟槽和导电布线沟槽，并且所述导电布线沟槽位于所述通孔沟槽上; 以及填充在所述沟槽中的导电层，其中所述导电层与所述器件结构电连接; 其中所述导电层包括由所述导电材料包围的导电材料和纳米管/线层。 其中，导电层包括由导电材料包围的导电材料和纳米管/线层。 该结构的导电层具有较好的导热性，导电性和较高的抗电迁移能力，能有效防止金属离子向外扩散。

公开(公告)号：US20120132923A1

公开(公告)日：2012-05-31

申请号：US13159351

申请日：2011-06-13

申请人： Huicai Zhong ,  Qingqing Liang ,  Haizhou Yin ,  Zhijiong Luo

发明人： Huicai Zhong ,  Qingqing Liang ,  Haizhou Yin ,  Zhijiong Luo

IPC分类号： H01L29/161 ,  H01L29/20 ,  H01L21/76

CPC分类号： H01L21/76232 ,  H01L21/7624 ,  H01L21/76283

摘要： The present invention relates to substrates for ICs and method for forming the same. The method comprises the steps of: forming a hard mask layer on the bulk silicon material; etching the hard mask layer and the bulk silicon material to form a first part for shallow trench isolation of at least one trench; forming a dielectric film on the sidewall of the at least one trench; further etching the bulk silicon material to deepen the at least one trench so as to form a second part of the at least one trench; completely oxidizing or nitridizing parts of the bulk silicon material which are between the second parts of the trenches, and parts of the bulk silicon material which are between the second parts of the trenches and side surfaces of the bulk silicon substrate; filling dielectric materials in the first and second parts of the at least one trench; and removing the hard mask layer.

摘要翻译： 本发明涉及IC的基板及其制造方法。 该方法包括以下步骤：在体硅材料上形成硬掩模层; 蚀刻硬掩模层和体硅材料以形成用于至少一个沟槽的浅沟槽隔离的第一部分; 在所述至少一个沟槽的侧壁上形成电介质膜; 进一步蚀刻体硅材料以加深所述至少一个沟槽，以便形成所述至少一个沟槽的第二部分; 在沟槽的第二部分之间的体硅材料的部分和沟槽的第二部分和体硅衬底的侧表面之间的体硅材料的部分完全氧化或氮化; 在所述至少一个沟槽的第一和第二部分中填充介电材料; 并除去硬掩模层。

公开(公告)号：US20110298053A1

公开(公告)日：2011-12-08

申请号：US12997625

申请日：2010-09-19

申请人： Huicai Zhong ,  Zhijiong Luo ,  Qingqing Liang

发明人： Huicai Zhong ,  Zhijiong Luo ,  Qingqing Liang

IPC分类号： H01L29/78 ,  H01L21/3205 ,  B82Y40/00 ,  B82Y99/00

CPC分类号： H01L29/513 ,  H01L21/28176 ,  H01L29/517 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/78

摘要： A manufacturing method of a gate stack with sacrificial oxygen-scavenging metal spacers includes: forming a gate stack structure consisting of an interfacial oxide layer, a high-K dielectric layer and a metal gate electrode, on a semiconductor substrate; conformally depositing a metal layer covering the semiconductor substrate and the gate stack structure; and selectively etching the metal layer to remove the portions of the metal layer covering the top surface of the gate stack structure and the semiconductor substrate, so as to only keep the sacrificial oxygen-scavenging metal spacers surrounding the gate stack structure in the outer periphery of the gate stack structure. A semiconductor device manufactured by this process.

摘要翻译： 具有牺牲氧清除金属间隔物的栅极堆叠的制造方法包括：在半导体衬底上形成由界面氧化物层，高K电介质层和金属栅电极组成的栅叠层结构; 保形地沉积覆盖半导体衬底和栅极堆叠结构的金属层; 并且选择性地蚀刻金属层以去除覆盖栅极堆叠结构和半导体衬底的顶表面的金属层的部分，以便仅将围绕栅极堆叠结构的牺牲氧清除金属间隔物保持在外部周边 门堆栈结构。 通过该方法制造的半导体器件。

公开(公告)号：US08716095B2

公开(公告)日：2014-05-06

申请号：US12997625

申请日：2010-09-19

申请人： Huicai Zhong ,  Zhijiong Luo ,  Qingqing Liang

发明人： Huicai Zhong ,  Zhijiong Luo ,  Qingqing Liang

IPC分类号： H01L21/336 ,  H01L29/78

CPC分类号： H01L29/513 ,  H01L21/28176 ,  H01L29/517 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/78

摘要： A manufacturing method of a gate stack with sacrificial oxygen-scavenging metal spacers includes: forming a gate stack structure consisting of an interfacial oxide layer, a high-K dielectric layer and a metal gate electrode, on a semiconductor substrate; conformally depositing a metal layer covering the semiconductor substrate and the gate stack structure; and selectively etching the metal layer to remove the portions of the metal layer covering the top surface of the gate stack structure and the semiconductor substrate, so as to only keep the sacrificial oxygen-scavenging metal spacers surrounding the gate stack structure in the outer periphery of the gate stack structure. A semiconductor device manufactured by this process.

摘要翻译： 具有牺牲氧清除金属间隔物的栅极堆叠的制造方法包括：在半导体衬底上形成由界面氧化物层，高K电介质层和金属栅电极组成的栅叠层结构; 保形地沉积覆盖半导体衬底和栅极堆叠结构的金属层; 并且选择性地蚀刻金属层以去除覆盖栅极堆叠结构和半导体衬底的顶表面的金属层的部分，以便仅将围绕栅极堆叠结构的牺牲氧清除金属间隔物保持在外部周边 门堆栈结构。 通过该方法制造的半导体器件。

公开(公告)号：US20120286373A1

公开(公告)日：2012-11-15

申请号：US13376501

申请日：2011-04-26

申请人： Huicai Zhong ,  Zhijiong Luo ,  Qingqing Liang

发明人： Huicai Zhong ,  Zhijiong Luo ,  Qingqing Liang

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/78 ,  H01L29/6653

摘要： Gates structures and methods for manufacturing the same are disclosed. In an example, the gate structure comprises a gate stack formed on a semiconductor substrate, the gate stack comprising a high-K dielectric layer and a metal gate electrode from bottom to top; a first dielectric layer on sidewalls of the gate stack, the first dielectric layer serving as first sidewall spacers; and a sacrificial metal layer on the first dielectric layer, the sacrificial metal layer serving as second sidewall spacers. The sacrificial metal layer in the gate structure reduces a thickness of an interfacial oxide layer in the step of annealing. The gate structure may be applied to a semiconductor device having a small size because the gate dielectric layer has a low EOT value.

摘要翻译： 公开了用于制造其门的结构和方法。 在一个示例中，栅极结构包括形成在半导体衬底上的栅极堆叠，栅堆叠包括从底部到顶部的高K电介质层和金属栅电极; 位于所述栅极叠层的侧壁上的第一介电层，所述第一介电层用作第一侧壁间隔物; 以及在所述第一电介质层上的牺牲金属层，所述牺牲金属层用作第二侧壁间隔物。 栅极结构中的牺牲金属层在退火步骤中减小界面氧化物层的厚度。 栅极结构可以应用于具有小尺寸的半导体器件，因为栅极介电层具有低的EOT值。

公开(公告)号：US09048286B2

公开(公告)日：2015-06-02

申请号：US13159351

申请日：2011-06-13

申请人： Huicai Zhong ,  Qingqing Liang ,  Haizhou Yin ,  Zhijiong Luo

发明人： Huicai Zhong ,  Qingqing Liang ,  Haizhou Yin ,  Zhijiong Luo

IPC分类号： H01L21/76 ,  H01L21/762

CPC分类号： H01L21/76232 ,  H01L21/7624 ,  H01L21/76283

摘要： The present invention relates to substrates for ICs and method for forming the same. The method comprises the steps of: forming a hard mask layer on the bulk silicon material; etching the hard mask layer and the bulk silicon material to form a first part for shallow trench isolation of at least one trench; forming a dielectric film on the sidewall of the at least one trench; further etching the bulk silicon material to deepen the at least one trench so as to form a second part of the at least one trench; completely oxidizing or nitridizing parts of the bulk silicon material which are between the second parts of the trenches, and parts of the bulk silicon material which are between the second parts of the trenches and side surfaces of the bulk silicon substrate; filling dielectric materials in the first and second parts of the at least one trench; and removing the hard mask layer.

摘要翻译： 本发明涉及IC的基板及其制造方法。 该方法包括以下步骤：在体硅材料上形成硬掩模层; 蚀刻硬掩模层和体硅材料以形成用于至少一个沟槽的浅沟槽隔离的第一部分; 在所述至少一个沟槽的侧壁上形成电介质膜; 进一步蚀刻体硅材料以加深所述至少一个沟槽，以便形成所述至少一个沟槽的第二部分; 在沟槽的第二部分之间的体硅材料的部分和沟槽的第二部分和体硅衬底的侧表面之间的体硅材料的部分完全氧化或氮化; 在所述至少一个沟槽的第一和第二部分中填充介电材料; 并除去硬掩模层。

公开(公告)号：US08410609B2

公开(公告)日：2013-04-02

申请号：US13129321

申请日：2011-02-26

申请人： Huicai Zhong ,  Qingqing Liang ,  Zhijiong Luo ,  Huilong Zhu

发明人： Huicai Zhong ,  Qingqing Liang ,  Zhijiong Luo ,  Huilong Zhu

IPC分类号： H01L29/40 ,  H01L21/00

CPC分类号： H01L23/53276 ,  H01L21/76807 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/76847 ,  H01L21/76877 ,  H01L2221/1094 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention relates to a semiconductor device structure and a method for manufacturing the same; the structure comprises: a semiconductor substrate on which a device structure is formed thereon; an interlayer dielectric layer formed on the device structure, wherein a trench is formed in the interlayer dielectric layer, the trench comprises an incorporated via trench and a conductive wiring trench, and the conductive wiring trench is positioned on the via trench; and a conductive layer filled in the trench, wherein the conductive layer is electrically connected with the device structure; wherein the conductive layer comprises a conductive material and a nanotube/wire layer surrounded by the conductive material. Wherein, the conductive layer comprises a conductive material and a nanotube/wire layer surrounded by the conductive material. The conductive layer of the structure has better thermal conductivity, conductivity and high anti-electromigration capability, thus is able to effectively prevent metal ions from diffusing outwards.

摘要翻译： 半导体器件结构及其制造方法技术领域本发明涉及半导体器件结构及其制造方法。 该结构包括：其上形成有器件结构的半导体衬底; 在所述器件结构上形成的层间电介质层，其中在所述层间介质层中形成沟槽，所述沟槽包括并入的通孔沟槽和导电布线沟槽，并且所述导电布线沟槽位于所述通孔沟槽上; 以及填充在所述沟槽中的导电层，其中所述导电层与所述器件结构电连接; 其中所述导电层包括由所述导电材料包围的导电材料和纳米管/线层。 其中，导电层包括由导电材料包围的导电材料和纳米管/线层。 该结构的导电层具有较好的导热性，导电性和较高的抗电迁移能力，能有效防止金属离子向外扩散。

公开(公告)号：US09419108B2

公开(公告)日：2016-08-16

申请号：US14406904

申请日：2012-08-17

申请人： Qingqing Liang ,  Huicai Zhong ,  Huilong Zhu ,  Chao Zhao ,  Tianchun Ye

发明人： Qingqing Liang ,  Huicai Zhong ,  Huilong Zhu ,  Chao Zhao ,  Tianchun Ye

IPC分类号： H01L29/66 ,  H01L29/78

CPC分类号： H01L29/66795 ,  H01L29/785 ,  H01L29/7855

摘要： One embodiment of present invention provides a method for manufacturing a semiconductor structure, which comprises: forming a gate stack on a semiconductor substrate and removing parts of the substrates situated on two sides of the gate stack; forming sidewall spacers on sidewalls of the gate stack and on sidewalls of the part of the substrate under the gate stack; forming doped regions in parts of the substrate on two sides of the gate stack, and forming a first dielectric layer to cover the entire semiconductor structure; selectively removing parts of the gate stack and parts of the first dielectric layer to form a channel region opening and source/drain region openings; forming a high K dielectric layer on sidewalls of the channel region opening; and implementing epitaxy process to form a continuous fin structure that spans across the channel region opening and the source/drain region openings.

摘要翻译： 本发明的一个实施例提供了一种用于制造半导体结构的方法，其包括：在半导体衬底上形成栅极叠层并去除位于栅极叠层两侧的衬底的部分; 在所述栅极堆叠的侧壁上以及在所述栅极堆叠下的所述衬底的所述部分的侧壁上形成侧壁间隔物; 在所述栅极堆叠的两侧上在所述衬底的部分中形成掺杂区域，以及形成覆盖整个半导体结构的第一介电层; 选择性地去除所述栅极堆叠的部分和所述第一介电层的部分以形成沟道区域开口和源极/漏极区域开口; 在沟道区域开口的侧壁上形成高K电介质层; 并且实现外延工艺以形成跨越沟道区域开口和源极/漏极区域开口的连续翅片结构。

公开(公告)号：US20150236134A1

公开(公告)日：2015-08-20

申请号：US14412237

申请日：2012-07-18

申请人： Huicai Zhong ,  Qingqing Liang ,  Chao Zhao

发明人： Huicai Zhong ,  Qingqing Liang ,  Chao Zhao

IPC分类号： H01L29/66

CPC分类号： H01L29/66795 ,  H01L21/268 ,  H01L21/76283 ,  H01L29/665 ,  H01L29/785

摘要： A method of manufacturing a FinFET semiconductor device is provided, wherein the semiconductor fins are formed in a parallel arrangement which intersects the gates arranged in parallel. The polycrystalline silicon layer is deposited and then converted into a single crystal silicon layer such that the single crystal silicon layer and the semiconductor fins are integrated in essence, i.e., the source/drain region in the semiconductor fins is raised and the top area of the semiconductor fins is extended. Subsequently, the single crystal silicon layer above the top of the semiconductor fins is converted into a metal silicide so as to form a source/drain region contact. The source/drain region contact in the present invention has a larger area than that in a conventional FinFET, which decreases the contact resistance and facilitates the formation of a self-aligned metal plug in the follow-up process.

摘要翻译： 提供一种制造FinFET半导体器件的方法，其中半导体鳍片形成为与并行布置的栅极相交的平行布置。 沉积多晶硅层，然后转换为单晶硅层，使得单晶硅层和半导体鳍片本质上是集成的，即半导体鳍片中的源极/漏极区域被升高，并且顶部区域 半导体鳍片延伸。 随后，将半导体鳍片顶部上方的单晶硅层转换为金属硅化物，以形成源极/漏极区域接触。 本发明中的源极/漏极区域的接触面积大于传统的FinFET的面积，这在以后的过程中降低了接触电阻并且有利于形成自对准的金属插塞。

公开(公告)号：US09012963B2

公开(公告)日：2015-04-21

申请号：US13501518

申请日：2011-11-18

申请人： Qingqing Liang ,  Miao Xu ,  Huilong Zhu ,  Huicai Zhong

发明人： Qingqing Liang ,  Miao Xu ,  Huilong Zhu ,  Huicai Zhong

IPC分类号： H01L29/66 ,  H01L29/786 ,  H01L29/49

CPC分类号： H01L29/78654 ,  H01L29/4908 ,  H01L29/78603 ,  H01L29/78648 ,  H01L29/78696

摘要： The present application discloses a semiconductor device comprising a source region and a drain region in an ultra-thin semiconductor layer; a channel region between the source region and the drain region in the ultra-thin semiconductor layer; a front gate stack above the channel region, the front gate comprising a front gate and a front gate dielectric between the front gate and the channel region; and a back gate stack below the channel region, the back gate stack comprising a back gate and a back gate dielectric between the back gate and the channel region, wherein the front gate is made of a high-Vt material, and the back gate is made of a low-Vt material. According to another embodiment, the front gate and the back gate are made of the same material, and the back gate is applied with a forward bias voltage during operation. The semiconductor device alleviates threshold voltage fluctuation due to varied thickness of the channel region by means of the back gate.

摘要翻译： 本申请公开了一种半导体器件，其包括超薄半导体层中的源极区域和漏极区域; 在超薄半导体层中的源极区域和漏极区域之间的沟道区域; 在所述沟道区域上方的前栅极堆叠，所述前栅极包括在所述前栅极和所述沟道区域之间的前栅极和前栅极电介质; 以及在沟道区域下方的背栅极堆叠，所述背栅叠层包括在所述背栅极和沟道区域之间的背栅极和背栅电介质，其中所述前栅极由高Vt材料制成，并且所述背栅极 由低Vt材料制成。 根据另一实施例，前栅极和后栅极由相同的材料制成，并且背栅在工作期间被施加正偏压。 半导体器件通过后栅极减小由沟道区域的厚度变化引起的阈值电压波动。