公开(公告)号：US09419108B2

公开(公告)日：2016-08-16

申请号：US14406904

申请日：2012-08-17

申请人： Qingqing Liang ,  Huicai Zhong ,  Huilong Zhu ,  Chao Zhao ,  Tianchun Ye

发明人： Qingqing Liang ,  Huicai Zhong ,  Huilong Zhu ,  Chao Zhao ,  Tianchun Ye

IPC分类号： H01L29/66 ,  H01L29/78

CPC分类号： H01L29/66795 ,  H01L29/785 ,  H01L29/7855

摘要： One embodiment of present invention provides a method for manufacturing a semiconductor structure, which comprises: forming a gate stack on a semiconductor substrate and removing parts of the substrates situated on two sides of the gate stack; forming sidewall spacers on sidewalls of the gate stack and on sidewalls of the part of the substrate under the gate stack; forming doped regions in parts of the substrate on two sides of the gate stack, and forming a first dielectric layer to cover the entire semiconductor structure; selectively removing parts of the gate stack and parts of the first dielectric layer to form a channel region opening and source/drain region openings; forming a high K dielectric layer on sidewalls of the channel region opening; and implementing epitaxy process to form a continuous fin structure that spans across the channel region opening and the source/drain region openings.

摘要翻译： 本发明的一个实施例提供了一种用于制造半导体结构的方法，其包括：在半导体衬底上形成栅极叠层并去除位于栅极叠层两侧的衬底的部分; 在所述栅极堆叠的侧壁上以及在所述栅极堆叠下的所述衬底的所述部分的侧壁上形成侧壁间隔物; 在所述栅极堆叠的两侧上在所述衬底的部分中形成掺杂区域，以及形成覆盖整个半导体结构的第一介电层; 选择性地去除所述栅极堆叠的部分和所述第一介电层的部分以形成沟道区域开口和源极/漏极区域开口; 在沟道区域开口的侧壁上形成高K电介质层; 并且实现外延工艺以形成跨越沟道区域开口和源极/漏极区域开口的连续翅片结构。

公开(公告)号：US20150295067A1

公开(公告)日：2015-10-15

申请号：US14004802

申请日：2012-12-07

申请人： Qiuxia Xu ,  Huilong Zhu ,  Huajie Zhou ,  Gaobo Xu ,  Qingqing Liang

发明人： Qiuxia Xu ,  Huilong Zhu ,  Huajie Zhou ,  Gaobo Xu ,  Qingqing Liang

IPC分类号： H01L29/66 ,  H01L21/28 ,  H01L29/423 ,  H01L29/51 ,  H01L21/02 ,  H01L21/265 ,  H01L29/49

CPC分类号： H01L29/66545 ,  H01L21/02181 ,  H01L21/02189 ,  H01L21/02192 ,  H01L21/02194 ,  H01L21/265 ,  H01L21/28088 ,  H01L21/28185 ,  H01L21/3215 ,  H01L29/42364 ,  H01L29/49 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/518 ,  H01L29/7833

摘要： The present disclosure discloses a method for manufacturing a P-type MOSFET, comprising: forming a part of the MOSFET on a semiconductor substrate, the part of the MOSFET comprising source/drain regions in the semiconductor substrate, a replacement gate stack between the source/drain regions above the semiconductor substrate, and a gate spacer surrounding the replacement gate stack; removing the replacement gate stack of the MOSFET to form a gate opening exposing a surface of the semiconductor substrate; forming an interface oxide layer on the exposed surface of the semiconductor; forming a high-K gate dielectric layer on the interface oxide layer in the gate opening; forming a first metal gate layer on the high-K gate dielectric layer; implanting dopant ions into the first metal gate layer; and performing annealing to cause the dopant ions to diffuse and accumulate at an upper interface between the high-K gate dielectric layer and the first metal gate layer and a lower interface between the high-K gate dielectric layer and the interface oxide layer, and also to generate electric dipoles by interfacial reaction at the lower interface between the high-K gate dielectric layer and the interface oxide layer.

摘要翻译： 本公开公开了一种用于制造P型MOSFET的方法，包括：在半导体衬底上形成MOSFET的一部分，所述MOSFET的部分包括半导体衬底中的源/漏区，源极/ 在半导体衬底之上的漏极区域和围绕替换栅极堆叠的栅极间隔; 去除MOSFET的替换栅极堆叠以形成暴露半导体衬底的表面的栅极开口; 在所述半导体的暴露表面上形成界面氧化物层; 在栅极开口中的界面氧化物层上形成高K栅极电介质层; 在高K栅极电介质层上形成第一金属栅极层; 将掺杂剂离子注入到第一金属栅极层中; 并且进行退火以使掺杂剂离子在高K栅极介电层和第一金属栅极层之间的上部界面以及高K栅极介电层和界面氧化物层之间的下部界面处扩散和积聚，并且还 通过界面反应在高K栅极介电层和界面氧化物层之间的下界面产生电偶极子。

公开(公告)号：US20150236134A1

公开(公告)日：2015-08-20

申请号：US14412237

申请日：2012-07-18

申请人： Huicai Zhong ,  Qingqing Liang ,  Chao Zhao

发明人： Huicai Zhong ,  Qingqing Liang ,  Chao Zhao

IPC分类号： H01L29/66

CPC分类号： H01L29/66795 ,  H01L21/268 ,  H01L21/76283 ,  H01L29/665 ,  H01L29/785

摘要： A method of manufacturing a FinFET semiconductor device is provided, wherein the semiconductor fins are formed in a parallel arrangement which intersects the gates arranged in parallel. The polycrystalline silicon layer is deposited and then converted into a single crystal silicon layer such that the single crystal silicon layer and the semiconductor fins are integrated in essence, i.e., the source/drain region in the semiconductor fins is raised and the top area of the semiconductor fins is extended. Subsequently, the single crystal silicon layer above the top of the semiconductor fins is converted into a metal silicide so as to form a source/drain region contact. The source/drain region contact in the present invention has a larger area than that in a conventional FinFET, which decreases the contact resistance and facilitates the formation of a self-aligned metal plug in the follow-up process.

摘要翻译： 提供一种制造FinFET半导体器件的方法，其中半导体鳍片形成为与并行布置的栅极相交的平行布置。 沉积多晶硅层，然后转换为单晶硅层，使得单晶硅层和半导体鳍片本质上是集成的，即半导体鳍片中的源极/漏极区域被升高，并且顶部区域 半导体鳍片延伸。 随后，将半导体鳍片顶部上方的单晶硅层转换为金属硅化物，以形成源极/漏极区域接触。 本发明中的源极/漏极区域的接触面积大于传统的FinFET的面积，这在以后的过程中降低了接触电阻并且有利于形成自对准的金属插塞。

公开(公告)号：US09012963B2

公开(公告)日：2015-04-21

申请号：US13501518

申请日：2011-11-18

申请人： Qingqing Liang ,  Miao Xu ,  Huilong Zhu ,  Huicai Zhong

发明人： Qingqing Liang ,  Miao Xu ,  Huilong Zhu ,  Huicai Zhong

IPC分类号： H01L29/66 ,  H01L29/786 ,  H01L29/49

CPC分类号： H01L29/78654 ,  H01L29/4908 ,  H01L29/78603 ,  H01L29/78648 ,  H01L29/78696

摘要： The present application discloses a semiconductor device comprising a source region and a drain region in an ultra-thin semiconductor layer; a channel region between the source region and the drain region in the ultra-thin semiconductor layer; a front gate stack above the channel region, the front gate comprising a front gate and a front gate dielectric between the front gate and the channel region; and a back gate stack below the channel region, the back gate stack comprising a back gate and a back gate dielectric between the back gate and the channel region, wherein the front gate is made of a high-Vt material, and the back gate is made of a low-Vt material. According to another embodiment, the front gate and the back gate are made of the same material, and the back gate is applied with a forward bias voltage during operation. The semiconductor device alleviates threshold voltage fluctuation due to varied thickness of the channel region by means of the back gate.

摘要翻译： 本申请公开了一种半导体器件，其包括超薄半导体层中的源极区域和漏极区域; 在超薄半导体层中的源极区域和漏极区域之间的沟道区域; 在所述沟道区域上方的前栅极堆叠，所述前栅极包括在所述前栅极和所述沟道区域之间的前栅极和前栅极电介质; 以及在沟道区域下方的背栅极堆叠，所述背栅叠层包括在所述背栅极和沟道区域之间的背栅极和背栅电介质，其中所述前栅极由高Vt材料制成，并且所述背栅极 由低Vt材料制成。 根据另一实施例，前栅极和后栅极由相同的材料制成，并且背栅在工作期间被施加正偏压。 半导体器件通过后栅极减小由沟道区域的厚度变化引起的阈值电压波动。

公开(公告)号：US08859378B2

公开(公告)日：2014-10-14

申请号：US13377141

申请日：2011-08-10

申请人： Qingqing Liang ,  Huicai Zhong ,  Huilong Zhu

发明人： Qingqing Liang ,  Huicai Zhong ,  Huilong Zhu

IPC分类号： H01L21/336 ,  H01L27/12 ,  H01L21/8234 ,  H01L21/84 ,  H01L27/088 ,  H01L29/66

CPC分类号： H01L27/1211 ,  H01L21/823431 ,  H01L21/845 ,  H01L27/0886 ,  H01L29/66545

摘要： Embodiments of the present invention disclose a method for manufacturing a Fin Field-Effect Transistor. When a fin is formed, a dummy gate across the fin is formed on the fin, a spacer is formed on sidewalls of the dummy gate, and a cover layer is formed on the first dielectric layer and on the fin outside the dummy gate and the spacer; then, an self-aligned and elevated source/drain region is formed at both sides of the dummy gate by the spacer, wherein the upper surfaces of the gate and the source/drain region are in the same plane. The upper surfaces of the gate and the source/drain region are in the same plane, making alignment of the contact plug easier; and the gate and the source/drain region are separated by the spacer, thereby improving alignment accuracy, solving inaccurate alignment of the contact plug, and improving device AC performance.

摘要翻译： 本发明的实施例公开了一种制造Fin场效应晶体管的方法。 当形成翅片时，在翅片上形成跨鳍片的虚拟栅极，在虚拟栅极的侧壁上形成间隔物，并且在第一介电层上形成覆盖层，并在模拟栅极外部形成覆盖层， 间隔物 然后，通过间隔件在虚拟栅极的两侧形成自对准和升高的源极/漏极区域，其中栅极和源极/漏极区域的上表面在同一平面内。 栅极和源极/漏极区域的上表面位于相同的平面中，使接触插塞的对准更容易; 并且栅极和源极/漏极区域被间隔物分开，从而提高对准精度，解决接触插塞的不准确的对准以及提高器件AC性能。

公开(公告)号：US08816392B2

公开(公告)日：2014-08-26

申请号：US13121998

申请日：2011-03-02

申请人： Huilong Zhu ,  Qingqing Liang

发明人： Huilong Zhu ,  Qingqing Liang

IPC分类号： H01L29/66 ,  H01L33/00 ,  H01L21/02

CPC分类号： H01L29/66 ,  B82Y10/00 ,  H01L21/02 ,  H01L21/28273 ,  H01L29/66795 ,  H01L29/66803 ,  H01L29/66825 ,  H01L29/785 ,  H01L33/00

摘要： A semiconductor device comprises a semiconductor substrate on an insulating layer; and a second gate that is located on the insulating layer and is embedded at least partially in the semiconductor substrate. A method for forming a semiconductor device comprises: forming a semiconductor substrate on an insulating layer; forming a void within the semiconductor substrate, with the insulating layer being exposed by the void; and forming a second gate, with the void being filled with at least one part of the second gate. It facilitates the reduction of the short channel effects, resistances of the source and drain regions, and parasitic capacitances.

摘要翻译： 半导体器件包括绝缘层上的半导体衬底; 以及第二栅极，其位于所述绝缘层上并且至少部分地嵌入所述半导体衬底中。 一种形成半导体器件的方法包括：在绝缘层上形成半导体衬底; 在半导体衬底内形成空隙，绝缘层被空隙暴露; 以及形成第二栅极，其中空隙填充有第二栅极的至少一部分。 它有助于减少短沟道效应，源极和漏极区域的电阻以及寄生电容。

公开(公告)号：US08815660B2

公开(公告)日：2014-08-26

申请号：US12700797

申请日：2010-02-05

申请人： Qingqing Liang ,  Huilong Zhu ,  Zhijiong Luo ,  Haizhou Yin

发明人： Qingqing Liang ,  Huilong Zhu ,  Zhijiong Luo ,  Haizhou Yin

IPC分类号： H01L29/786

CPC分类号： H01L27/1203 ,  H01L21/8221 ,  H01L21/84 ,  H01L27/0688 ,  H01L29/6675 ,  H01L29/78615 ,  H01L29/78624 ,  H01L29/78687

摘要： The present invention generally relates to a semiconductor structure and method, and more specifically, to a structure and method for reducing floating body effect of silicon on insulator (SOI) metal oxide semiconductor field effect transistors (MOSFETs). An integrated circuit (IC) structure includes a SOI substrate and at least one MOSFET formed on the SOI substrate. Additionally, the IC structure includes an asymmetrical source-drain junction in the at least one MOSFET by damaging a pn junction to reduce floating body effects of the at least one MOSFET.

摘要翻译： 本发明一般涉及半导体结构和方法，更具体地说，涉及用于减少绝缘体上硅（SOI）金属氧化物半导体场效应晶体管（MOSFET）的浮体效应的结构和方法。 集成电路（IC）结构包括SOI衬底和形成在SOI衬底上的至少一个MOSFET。 此外，IC结构包括通过损坏pn结在至少一个MOSFET中的不对称源极 - 漏极结，以减少至少一个MOSFET的浮体效应。

公开(公告)号：US08748983B2

公开(公告)日：2014-06-10

申请号：US13380828

申请日：2011-08-12

申请人： Huicai Zhong ,  Chao Zhao ,  Qingqing Liang

发明人： Huicai Zhong ,  Chao Zhao ,  Qingqing Liang

IPC分类号： H01L27/12 ,  H01L21/70

CPC分类号： H01L29/0847 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/78 ,  H01L29/7848

摘要： An embedded source/drain MOS transistor and a formation method thereof are provided. The embedded source/drain MOS transistor comprises: a semiconductor substrate; a gate structure on the semiconductor substrate; and a source/drain stack embedded in the semiconductor substrate at both sides of the gate structure with an upper surface of the source/drain stack being exposed, wherein the source/drain stack comprises a dielectric layer and a semiconductor layer above the dielectric layer. The present invention can cut off the path for the leakage current from the source region and the drain region to the semiconductor substrate, thereby reducing the leakage current from the source region and the drain region to the semiconductor substrate.

摘要翻译： 提供一种嵌入式源极/漏极MOS晶体管及其形成方法。 嵌入式源极/漏极MOS晶体管包括：半导体衬底; 半导体衬底上的栅极结构; 以及在源极/漏极叠层的上表面被暴露的栅极结构的两侧嵌入在半导体衬底中的源极/漏极堆叠，其中源极/漏极叠层包括电介质层和介电层上方的半导体层。 本发明可以切断从源极区域和漏极区域到半导体衬底的漏电流的路径，从而减少从源极区域和漏极区域到半导体衬底的漏电流。

公开(公告)号：US20140124847A1

公开(公告)日：2014-05-08

申请号：US14151441

申请日：2014-01-09

申请人： Huilong Zhu ,  Qingqing Liang ,  Huicai Zhong

发明人： Huilong Zhu ,  Qingqing Liang ,  Huicai Zhong

IPC分类号： H01L29/788 ,  H01L21/28 ,  H01L29/66

CPC分类号： H01L29/66825 ,  H01L21/28273 ,  H01L29/42324 ,  H01L29/7881

摘要： Semiconductor devices and methods for manufacturing the same are disclosed. In one aspect, the method comprises forming a first shielding layer on a substrate, and forming one of source and drain regions with the first shielding layer as a mask. Then, forming a second shielding layer on the substrate, and forming the other of the source and drain regions with the second shielding layer as a mask. Then, removing a portion of the second shielding layer which is next to the other of the source and drain regions. Lastly, forming a first gate dielectric layer, a floating gate layer, and a second gate dielectric layer, and forming a gate conductor as a spacer on a sidewall of a remaining portion of the second shielding layer.

摘要翻译： 公开了半导体装置及其制造方法。 一方面，该方法包括在衬底上形成第一屏蔽层，并且将第一屏蔽层作为掩模形成源区和漏区之一。 然后，在衬底上形成第二屏蔽层，并且用第二屏蔽层作为掩模形成源区和漏区中的另一个。 然后，去除位于源区和漏区另一个旁边的第二屏蔽层的一部分。 最后，形成第一栅极电介质层，浮栅层和第二栅极电介质层，并在第二屏蔽层的剩余部分的侧壁上形成作为间隔物的栅极导体。

公开(公告)号：US08716799B2

公开(公告)日：2014-05-06

申请号：US13376996

申请日：2011-08-01

申请人： Huilong Zhu ,  Miao Xu ,  Qingqing Liang

发明人： Huilong Zhu ,  Miao Xu ,  Qingqing Liang

IPC分类号： H01L27/01 ,  H01L27/12 ,  H01L31/0392

CPC分类号： H01L29/78648 ,  H01L21/2652

摘要： The present application discloses a MOSFET and a method for manufacturing the same, wherein the MOSFET comprises: an SOI wafer, which comprises a semiconductor substrate, a buried insulator layer, and a semiconductor layer, the buried insulator layer being disposed on the semiconductor substrate, and the semiconductor layer being disposed on the buried insulator layer; a gate stack, which is disposed on the semiconductor layer; a source region and a drain region, which are disposed in the semiconductor layer and on opposite sides of the gate stack; and a channel region, which are disposed in the semiconductor layer and sandwiched by the source region and the drain region, wherein the MOSFET further comprises a back gate disposed in the semiconductor substrate, and wherein the back gate comprises first, second and third compensation doping regions, the first compensation doping region is disposed under the source region and the drain region; the second compensation doping region extends in a direction away from the channel region and adjoining the first compensation doping region; and the third compensation doping region is disposed under the channel region and adjoining the first compensation doping region. By changing the doping type of the back gate, the MOSFET can have an adjustable threshold voltage, and can have a reduced parasitic capacitance and a reduced contact resistance in connection with the back gate.

摘要翻译： 本申请公开了一种MOSFET及其制造方法，其中，所述MOSFET包括：SOI晶片，其包含半导体基板，埋入绝缘体层和半导体层，所述埋入绝缘体层设置在所述半导体基板上， 并且所述半导体层设置在所述埋入绝缘体层上; 栅极堆叠，其设置在半导体层上; 源极区域和漏极区域，其设置在所述半导体层中并且在所述栅极堆叠的相对侧上; 以及沟道区域，其设置在所述半导体层中并且被所述源极区域和所述漏极区域夹持，其中所述MOSFET还包括设置在所述半导体衬底中的背栅极，并且其中所述后栅极包括第一，第二和第三补偿掺杂 第一补偿掺杂区域设置在源极区域和漏极区域下方; 所述第二补偿掺杂区域在远离所述沟道区域并邻接所述第一补偿掺杂区域的方向上延伸; 并且第三补偿掺杂区域设置在沟道区域的下方并与第一补偿掺杂区域相邻。 通过改变背栅的掺杂类型，MOSFET可以具有可调的阈值电压，并且可以具有减小的寄生电容和与后栅极相关联的降低的接触电阻。