公开(公告)号：US20050215017A1

公开(公告)日：2005-09-29

申请号：US10807081

申请日：2004-03-23

申请人： Hung-Wei Chen ,  Hsun-Chin Tsao ,  Kuang-Hsin Chen ,  Di-Houng Lee

发明人： Hung-Wei Chen ,  Hsun-Chin Tsao ,  Kuang-Hsin Chen ,  Di-Houng Lee

IPC分类号： H01L21/336 ,  H01L21/762 ,  H01L21/84 ,  H01L27/12 ,  H01L29/786

CPC分类号： H01L21/76243 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/78603

摘要： Methods of reducing a short channel phenomena for an NMOS device formed in an SOI layer, wherein the short channel phenomena is created by boron movement from a channel region to adjacent insulator regions, has been developed. A first embodiment of this invention entails the formation of a boron or nitrogen doped insulator layer located underlying the NMOS device. This is accomplished via formation of shallow trench openings in composite silicon nitride—silicon shapes, followed by lateral pull back of the silicon nitride shapes exposing portions of the top surface of the silicon shapes, followed by implantation of boron or nitrogen ions into portions of the insulator layer exposed in the STI openings and into portions of the insulator layer underlying exposed portions of the silicon shapes. A subsequent hydrogen anneal procedure finalizes the doped insulator layer which alleviates boron segregation from an overlying NMOS channel region. A second embodiment features the formation of a dielectric barrier layer on the surfaces of STI openings preventing boron from segregated to silicon oxide filled STI regions. A combination of both embodiments can be employed to reduce and prevent boron segregation to both underlying and adjacent insulator regions, thus reducing the risk of short channel phenomena.

摘要翻译： 已经开发了减少在SOI层中形成的NMOS器件的短通道现象的方法，其中通过硼从沟道区域移动到相邻的绝缘体区域产生短沟道现象。 本发明的第一实施例需要形成位于NMOS器件下面的硼或氮掺杂的绝缘体层。 这是通过在复合氮化硅 - 硅形状中形成浅沟槽开口而实现的，随后氮化硅形状的横向拉回暴露出硅形状的顶表面的部分，然后将硼或氮离子注入到 绝缘体层暴露在STI开口中并且沉积在硅形状的暴露部分下面的绝缘体层的部分中。 随后的氢退火程序完成掺杂的绝缘体层，其减轻了从上覆的NMOS沟道区域的硼偏析。 第二实施例的特征在于在STI开口的表面上形成介电阻挡层，防止硼偏析到填充氧化硅的STI区域。 可以采用两种实施方案的组合来减少和防止硼分离到下面的和相邻的绝缘体区域，从而降低短沟道现象的风险。

公开(公告)号：US07074692B2

公开(公告)日：2006-07-11

申请号：US10807081

申请日：2004-03-23

申请人： Hung-Wei Chen ,  Hsun-Chin Tsao ,  Kuang-Hsin Chen ,  Di-Houng Lee

发明人： Hung-Wei Chen ,  Hsun-Chin Tsao ,  Kuang-Hsin Chen ,  Di-Houng Lee

IPC分类号： H01L21/76

CPC分类号： H01L21/76243 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/78603

摘要： Methods of reducing a short channel phenomena for an NMOS device formed in an SOI layer, wherein the short channel phenomena is created by boron movement from a channel region to adjacent insulator regions, has been developed. A first embodiment of this invention entails the formation of a boron or nitrogen doped insulator layer located underlying the NMOS device. This is accomplished via formation of shallow trench openings in composite silicon nitride-silicon shapes, followed by lateral pull back of the silicon nitride shapes exposing portions of the top surface of the silicon shapes, followed by implantation of boron or nitrogen ions into portions of the insulator layer exposed in the STI openings and into portions of the insulator layer underlying exposed portions of the silicon shapes. A subsequent hydrogen anneal procedure finalizes the doped insulator layer which alleviates boron segregation from an overlying NMOS channel region. A second embodiment features the formation of a dielectric barrier layer on the surfaces of STI openings preventing boron from segregated to silicon oxide filled STI regions. A combination of both embodiments can be employed to reduce and prevent boron segregation to both underlying and adjacent insulator regions, thus reducing the risk of short channel phenomena.

摘要翻译： 已经开发了减少在SOI层中形成的NMOS器件的短通道现象的方法，其中通过硼从沟道区域移动到相邻的绝缘体区域产生短沟道现象。 本发明的第一实施例需要形成位于NMOS器件下面的硼或氮掺杂的绝缘体层。 这是通过在复合氮化硅 - 硅形状中形成浅沟槽开口而实现的，随后氮化硅形状的横向拉回暴露出硅形状的顶表面的部分，然后将硼或氮离子注入到 绝缘体层暴露在STI开口中并且沉积在硅形状的暴露部分下面的绝缘体层的部分中。 随后的氢退火程序完成掺杂的绝缘体层，其减轻了从上覆的NMOS沟道区域的硼偏析。 第二实施例的特征在于在STI开口的表面上形成介电阻挡层，防止硼偏析到填充氧化硅的STI区域。 可以采用两种实施方案的组合来减少和防止硼分离到下面的和相邻的绝缘体区域，从而降低短沟道现象的风险。

公开(公告)号：US07538351B2

公开(公告)日：2009-05-26

申请号：US11089405

申请日：2005-03-23

申请人： Hung-Wei Chen ,  Hsun-Chih Tsao ,  Kuang-Hsin Chen ,  Di-Hong Lee

发明人： Hung-Wei Chen ,  Hsun-Chih Tsao ,  Kuang-Hsin Chen ,  Di-Hong Lee

IPC分类号： H01L29/10

CPC分类号： H01L29/045 ,  H01L21/823807 ,  H01L21/84 ,  H01L27/0251 ,  H01L27/1203 ,  H01L27/1207 ,  H01L29/7843 ,  H01L29/7851 ,  H01L29/7854

摘要： A semiconductor device and method for forming the same including improved electrostatic discharge protection for advanced semiconductor devices, the semiconductor device including providing semiconductor substrate having a pre-selected surface orientation and crystal direction; an insulator layer overlying the semiconductor substrate; a first semiconductor active region overlying the insulator layer having a first surface orientation selected from the group consisting of and ; a second semiconductor active region extending through a thickness portion of the insulator layer having a second surface orientation selected from the group consisting of and different from the first surface orientation; wherein MOS devices including a first MOS device of a first conduction type is disposed on the first semiconductor active region and a second MOS device of a second conduction type is disposed on the second semiconductor active region.

摘要翻译： 一种半导体器件及其制造方法，包括提供先进半导体器件的改进的静电放电保护，所述半导体器件包括提供具有预选择的表面取向和晶体方向的半导体衬底; 覆盖半导体衬底的绝缘体层; 覆盖绝缘体层的第一半导体有源区具有选自<100>和<110>的第一表面取向; 延伸穿过绝缘体层的厚度部分的第二半导体有源区，其具有选自与第一表面取向不同的<110>和<100>的第二表面取向; 其中包括第一导电类型的第一MOS器件的MOS器件设置在第一半导体有源区上，并且第二导电类型的第二MOS器件设置在第二半导体有源区上。

公开(公告)号：US20070272954A1

公开(公告)日：2007-11-29

申请号：US11441724

申请日：2006-05-27

申请人： Kuang-Hsin Chen ,  Hsun-Chih Tsao ,  Jhi-Cherng Lu ,  Chuan-Ping Hou ,  Peng-Fu Hsu ,  Hung-Wei Chen ,  Di-Hong Lee

发明人： Kuang-Hsin Chen ,  Hsun-Chih Tsao ,  Jhi-Cherng Lu ,  Chuan-Ping Hou ,  Peng-Fu Hsu ,  Hung-Wei Chen ,  Di-Hong Lee

IPC分类号： H01L29/76

CPC分类号： H01L29/7851 ,  H01L29/66795

摘要： A fin-FET device and a method for fabrication thereof both employ a bulk semiconductor substrate. A fin and an adjoining trough are formed within the bulk semiconductor substrate. The trough is partially backfilled with a deposited dielectric layer to form an exposed fin region and an unexposed fin region. A gate dielectric layer is formed upon the exposed fin region and a gate electrode is formed upon the gate dielectric layer. By employing a bulk semiconductor substrate the fin-FET device is fabricated cost effectively.

摘要翻译： 翅片FET器件及其制造方法都采用体半导体衬底。 在体半导体衬底内形成翅片和相邻的槽。 槽部分地用沉积的介电层回填以形成暴露的翅片区域和未曝光的翅片区域。 在暴露的散热片区域上形成栅极电介质层，在栅极电介质层上形成栅电极。 通过采用体半导体衬底，成本有效地制造了鳍式FET器件。

公开(公告)号：US20050145937A1

公开(公告)日：2005-07-07

申请号：US10747494

申请日：2003-12-29

申请人： Kuang-Hsin Chen ,  Hsun-Chih Tsao ,  Hung-Wei Chen ,  Di-Hong Lee ,  Chuan-Ping Hou ,  Jhi-Cherng Lu

发明人： Kuang-Hsin Chen ,  Hsun-Chih Tsao ,  Hung-Wei Chen ,  Di-Hong Lee ,  Chuan-Ping Hou ,  Jhi-Cherng Lu

IPC分类号： H01L21/00 ,  H01L21/20 ,  H01L21/762 ,  H01L21/84 ,  H01L27/01

CPC分类号： H01L21/76224 ,  H01L21/84

摘要： In a method of manufacturing a semiconductor device, an initial structure is provided. The initial structure includes a substrate, a patterned silicon layer, and a covering layer. The substrate has a buried insulator layer formed thereon. The patterned silicon layer is formed on the buried insulator layer. The covering layer is formed on the patterned silicon layer. A first layer is formed on the initial structure. Part of the first layer is removed with an etching process, such that a sidewall portion of the patterned silicon layer is exposed and such that a remaining portion of the first layer remains at a corner where the patterned silicon layer interfaces with the buried insulator layer. An oxide liner is formed on the exposed sidewall portion. A recess may be formed in the buried insulator layer (prior to forming the first layer) and may extend partially beneath the patterned silicon layer.

公开(公告)号：US07205601B2

公开(公告)日：2007-04-17

申请号：US11148903

申请日：2005-06-09

申请人： Di-Hong Lee ,  Hsun-Chih Tsao ,  Kuang-Hsin Chen ,  Hung-Wei Chen

发明人： Di-Hong Lee ,  Hsun-Chih Tsao ,  Kuang-Hsin Chen ,  Hung-Wei Chen

IPC分类号： H01L29/788

CPC分类号： H01L29/7881 ,  H01L21/28273 ,  H01L29/42328 ,  H01L29/66795 ,  H01L29/66825 ,  H01L29/785

摘要： A FinFET split gate EEPROM structure includes a semiconductor substrate and an elongated semiconductor fin extending above the substrate. A control gate straddles the fin, the fin's sides and a first drain-proximate portion of a channel between a source and drain in the fin. The control gate includes a tunnel layer and a floating electrode over which are a first insulative stratum and a first conductive stratum. A select gate straddles the fin and its sides and a second, source-promixate portion of the channel. The select gate includes a second insulative stratum and a second conductive stratum. The insulative strata are portions of a continuous insulative layer covering the substrate and the fin. The conductive strata are electrically continuous portions of a continuous conductive layer formed on the insulative layer.

摘要翻译： FinFET分离栅极EEPROM结构包括半导体衬底和在衬底上延伸的细长半导体鳍片。 控制栅极横跨鳍片，翅片的侧面以及翅片中的源极和漏极之间的通道的第一漏极 - 近似部分。 控制门包括隧道层和浮动电极，第一绝缘层和第一导电层在其上形成。 选择栅极横跨鳍片及其侧面以及通道的第二个源极扩展部分。 选择门包括第二绝缘层和第二导电层。 绝缘层是覆盖基板和翅片的连续绝缘层的部分。 导电层是形成在绝缘层上的连续导电层的电连续部分。

公开(公告)号：US20060012004A1

公开(公告)日：2006-01-19

申请号：US11221200

申请日：2005-09-07

申请人： Kuang-Hsin Chen ,  Hsun-Chih Tsao ,  Hung-Wei Chen ,  Di-Hong Lee ,  Chuan-Ping Hou ,  Jhi-Cherng Lu

发明人： Kuang-Hsin Chen ,  Hsun-Chih Tsao ,  Hung-Wei Chen ,  Di-Hong Lee ,  Chuan-Ping Hou ,  Jhi-Cherng Lu

IPC分类号： H01L29/00 ,  H01L21/20

CPC分类号： H01L21/76224 ,  H01L21/84

摘要： In a method of manufacturing a semiconductor device, an initial structure is provided. The initial structure includes a substrate, a patterned silicon layer, and a covering layer. The substrate has a buried insulator layer formed thereon. The patterned silicon layer is formed on the buried insulator layer. The covering layer is formed on the patterned silicon layer. A first layer is formed on the initial structure. Part of the first layer is removed with an etching process, such that a sidewall portion of the patterned silicon layer is exposed and such that a remaining portion of the first layer remains at a corner where the patterned silicon layer interfaces with the buried insulator layer. An oxide liner is formed on the exposed sidewall portion. A recess may be formed in the buried insulator layer (prior to forming the first layer) and may extend partially beneath the patterned silicon layer.

摘要翻译： 在制造半导体器件的方法中，提供初始结构。 初始结构包括衬底，图案化硅层和覆盖层。 基板上形成有埋置的绝缘体层。 图案化的硅层形成在掩埋绝缘体层上。 覆盖层形成在图案化硅层上。 在初始结构上形成第一层。 通过蚀刻工艺去除第一层的一部分，使得图案化硅层的侧壁部分被暴露，并且使得第一层的剩余部分保留在图案化硅层与掩埋绝缘体层接合的拐角处。 在暴露的侧壁部分上形成氧化物衬垫。 可以在掩埋绝缘体层（在形成第一层之前）形成凹部，并且可以在图案化的硅层的部分下方延伸。

公开(公告)号：US06955955B2

公开(公告)日：2005-10-18

申请号：US10747494

申请日：2003-12-29

申请人： Kuang-Hsin Chen ,  Hsun-Chih Tsao ,  Hung-Wei Chen ,  Di-Hong Lee ,  Chuan-Ping Hou ,  Jhi-Cherng Lu

发明人： Kuang-Hsin Chen ,  Hsun-Chih Tsao ,  Hung-Wei Chen ,  Di-Hong Lee ,  Chuan-Ping Hou ,  Jhi-Cherng Lu

IPC分类号： H01L21/00 ,  H01L21/20 ,  H01L21/762 ,  H01L21/84 ,  H01L27/01

CPC分类号： H01L21/76224 ,  H01L21/84

摘要： In a method of manufacturing a semiconductor device, an initial structure is provided. The initial structure includes a substrate, a patterned silicon layer, and a covering layer. The substrate has a buried insulator layer formed thereon. The patterned silicon layer is formed on the buried insulator layer. The covering layer is formed on the patterned silicon layer. A first layer is formed on the initial structure. Part of the first layer is removed with an etching process, such that a sidewall portion of the patterned silicon layer is exposed and such that a remaining portion of the first layer remains at a corner where the patterned silicon layer interfaces with the buried insulator layer. An oxide liner is formed on the exposed sidewall portion. A recess may be formed in the buried insulator layer (prior to forming the first layer) and may extend partially beneath the patterned silicon layer.

摘要翻译： 在制造半导体器件的方法中，提供了初始结构。 初始结构包括衬底，图案化硅层和覆盖层。 基板上形成有埋置的绝缘体层。 图案化的硅层形成在掩埋绝缘体层上。 覆盖层形成在图案化硅层上。 在初始结构上形成第一层。 通过蚀刻工艺去除第一层的一部分，使得图案化硅层的侧壁部分被暴露，并且使得第一层的剩余部分保留在图案化硅层与掩埋绝缘体层接合的拐角处。 在暴露的侧壁部分上形成氧化物衬垫。 可以在掩埋绝缘体层（在形成第一层之前）形成凹部，并且可以在图案化的硅层的部分下方延伸。

公开(公告)号：US07663185B2

公开(公告)日：2010-02-16

申请号：US11441724

申请日：2006-05-27

申请人： Kuang-Hsin Chen ,  Hsun-Chih Tsao ,  Jhi-Cherng Lu ,  Chuan-Ping Hou ,  Peng-Fu Hsu ,  Hung-Wei Chen ,  Di-Hong Lee

发明人： Kuang-Hsin Chen ,  Hsun-Chih Tsao ,  Jhi-Cherng Lu ,  Chuan-Ping Hou ,  Peng-Fu Hsu ,  Hung-Wei Chen ,  Di-Hong Lee

IPC分类号： H01L29/76

CPC分类号： H01L29/7851 ,  H01L29/66795

摘要： A fin-FET device and a method for fabrication thereof both employ a bulk semiconductor substrate. A fin and an adjoining trough are formed within the bulk semiconductor substrate. The trough is partially backfilled with a deposited dielectric layer to form an exposed fin region and an unexposed fin region. A gate dielectric layer is formed upon the exposed fin region and a gate electrode is formed upon the gate dielectric layer. By employing a bulk semiconductor substrate the fin-FET device is fabricated cost effectively.

摘要翻译： 翅片FET器件及其制造方法都采用体半导体衬底。 在体半导体衬底内形成翅片和相邻的槽。 槽部分地用沉积的介电层回填以形成暴露的翅片区域和未曝光的翅片区域。 在暴露的散热片区域上形成栅极电介质层，在栅极电介质层上形成栅电极。 通过采用体半导体衬底，成本有效地制造了鳍式FET器件。

公开(公告)号：US07332777B2

公开(公告)日：2008-02-19

申请号：US11221200

申请日：2005-09-07

申请人： Kuang-Hsin Chen ,  Hsun-Chih Tsao ,  Hung-Wei Chen ,  Di-Hong Lee ,  Chuan-Ping Hou ,  Jhi-Cherng Lu

发明人： Kuang-Hsin Chen ,  Hsun-Chih Tsao ,  Hung-Wei Chen ,  Di-Hong Lee ,  Chuan-Ping Hou ,  Jhi-Cherng Lu

IPC分类号： H01L31/0392

CPC分类号： H01L21/76224 ,  H01L21/84

摘要： In a method of manufacturing a semiconductor device, an initial structure is provided. The initial structure includes a substrate, a patterned silicon layer, and a covering layer. The substrate has a buried insulator layer formed thereon. The patterned silicon layer is formed on the buried insulator layer. The covering layer is formed on the patterned silicon layer. A first layer is formed on the initial structure. Part of the first layer is removed with an etching process, such that a sidewall portion of the patterned silicon layer is exposed and such that a remaining portion of the first layer remains at a corner where the patterned silicon layer interfaces with the buried insulator layer. An oxide liner is formed on the exposed sidewall portion. A recess may be formed in the buried insulator layer (prior to forming the first layer) and may extend partially beneath the patterned silicon layer.

摘要翻译： 在制造半导体器件的方法中，提供了初始结构。 初始结构包括衬底，图案化硅层和覆盖层。 基板上形成有埋置的绝缘体层。 图案化的硅层形成在掩埋绝缘体层上。 覆盖层形成在图案化硅层上。 在初始结构上形成第一层。 通过蚀刻工艺去除第一层的一部分，使得图案化硅层的侧壁部分被暴露，并且使得第一层的剩余部分保留在图案化硅层与掩埋绝缘体层接合的拐角处。 在暴露的侧壁部分上形成氧化物衬垫。 可以在掩埋绝缘体层（在形成第一层之前）形成凹部，并且可以在图案化的硅层的部分下方延伸。