公开(公告)号：US20060192906A1

公开(公告)日：2006-08-31

申请号：US11356853

申请日：2006-02-17

申请人： Hye-Young Ryu ,  Jang-Soo Kim ,  Sang-Gab Kim ,  Hong-Kee Chin ,  Min-Seok Oh ,  Hee-Hwan Choe ,  Shi-Yul Kim

发明人： Hye-Young Ryu ,  Jang-Soo Kim ,  Sang-Gab Kim ,  Hong-Kee Chin ,  Min-Seok Oh ,  Hee-Hwan Choe ,  Shi-Yul Kim

IPC分类号： G02F1/136

CPC分类号： G02F1/136286 ,  G02F1/133345 ,  G02F1/1362 ,  G02F2001/136222 ,  G02F2202/02

摘要： A thin film transistor array panel is provided, which includes a gate line, a data line intersecting the gate line, a storage electrode apart from the gate and data lines, a thin film transistor connected to the gate and data lines and having a drain electrode, a pixel electrode connected to the drain electrode, a first insulating layer over the thin film transistor and disposed under the pixel electrode, and a second insulating layer disposed on the first insulating layer and having an opening exposing the first insulating layer on the storage electrode.

摘要翻译： 提供薄膜晶体管阵列面板，其包括栅极线，与栅极线相交的数据线，与栅极和数据线分开的存储电极，连接到栅极和数据线并具有漏极的薄膜晶体管 连接到漏电极的像素电极，薄膜晶体管上的第一绝缘层，并且设置在像素电极下方;第二绝缘层，设置在第一绝缘层上，并且具有使存储电极上的第一绝缘层露出的开口 。

公开(公告)号：US08305507B2

公开(公告)日：2012-11-06

申请号：US11356853

申请日：2006-02-17

申请人： Hye-Young Ryu ,  Jang-Soo Kim ,  Sang-Gab Kim ,  Hong-Kee Chin ,  Min-Seok Oh ,  Hee-Hwan Choe ,  Shi-Yul Kim

发明人： Hye-Young Ryu ,  Jang-Soo Kim ,  Sang-Gab Kim ,  Hong-Kee Chin ,  Min-Seok Oh ,  Hee-Hwan Choe ,  Shi-Yul Kim

IPC分类号： G02F1/1343

CPC分类号： G02F1/136286 ,  G02F1/133345 ,  G02F1/1362 ,  G02F2001/136222 ,  G02F2202/02

摘要： A thin film transistor array panel is provided, which includes a gate line, a data line intersecting the gate line, a storage electrode apart from the gate and data lines, a thin film transistor connected to the gate and data lines and having a drain electrode, a pixel electrode connected to the drain electrode, a first insulating layer over the thin film transistor and disposed under the pixel electrode, and a second insulating layer disposed on the first insulating layer and having an opening exposing the first insulating layer on the storage electrode.

摘要翻译： 提供薄膜晶体管阵列面板，其包括栅极线，与栅极线相交的数据线，与栅极和数据线分开的存储电极，连接到栅极和数据线并具有漏极的薄膜晶体管 连接到漏电极的像素电极，薄膜晶体管上的第一绝缘层，并且设置在像素电极下方;第二绝缘层，设置在第一绝缘层上，并且具有使存储电极上的第一绝缘层露出的开口 。

公开(公告)号：US07888675B2

公开(公告)日：2011-02-15

申请号：US12099718

申请日：2008-04-08

申请人： Sang-Gab Kim ,  Woo-Geun Lee ,  Shi-Yul Kim ,  Jin-Ho Ju ,  Jang-Soo Kim ,  Sang-Woo Whangbo ,  Min-Seok Oh ,  Hye-Young Ryu ,  Hong-Kee Chin

发明人： Sang-Gab Kim ,  Woo-Geun Lee ,  Shi-Yul Kim ,  Jin-Ho Ju ,  Jang-Soo Kim ,  Sang-Woo Whangbo ,  Min-Seok Oh ,  Hye-Young Ryu ,  Hong-Kee Chin

IPC分类号： H01L21/00

CPC分类号： H01L27/124 ,  G02F2001/13629 ,  H01L29/458

摘要： The present invention provides a manufacturing method of a thin film transistor array panel, which includes forming a gate line on a substrate; forming a gate insulating layer, a semiconductor layer, and an ohmic contact on the gate line; forming a first conducting film including Mo, a second conducting film including Al, and a third conducting film including Mo on the ohmic contact; forming a first photoresist pattern on the third conducting film; etching the first, second, and third conducting films, the ohmic contact, and the semiconductor layer using the first photoresist pattern as a mask; removing the first photoresist pattern by a predetermined thickness to form a second photoresist pattern; etching the first, second, and third conducting films using the second photoresist pattern as a mask to expose a portion of the ohmic contact; and etching the exposed ohmic contact using a Cl-containing gas and a F-containing gas.

摘要翻译： 本发明提供一种薄膜晶体管阵列面板的制造方法，其包括在基板上形成栅极线; 在栅极线上形成栅极绝缘层，半导体层和欧姆接触; 形成包括Mo的第一导电膜，包括Al的第二导电膜和在欧姆接触上包含Mo的第三导电膜; 在所述第三导电膜上形成第一光致抗蚀剂图案; 使用第一光致抗蚀剂图案作为掩模蚀刻第一，第二和第三导电膜，欧姆接触和半导体层; 将第一光致抗蚀剂图案去除预定厚度以形成第二光致抗蚀剂图案; 使用第二光致抗蚀剂图案作为掩模蚀刻第一，第二和第三导电膜以暴露欧姆接触的一部分; 并使用含Cl气体和含F气体蚀刻暴露的欧姆接触。

公开(公告)号：US07371621B2

公开(公告)日：2008-05-13

申请号：US11486330

申请日：2006-07-12

申请人： Sang-Gab Kim ,  Woo-Geun Lee ,  Shi-Yul Kim ,  Jin-Ho Ju ,  Jang-Soo Kim ,  Sang-Woo Whangbo ,  Min-Seok Oh ,  Hye-Young Ryu ,  Hong-Kee Chin

发明人： Sang-Gab Kim ,  Woo-Geun Lee ,  Shi-Yul Kim ,  Jin-Ho Ju ,  Jang-Soo Kim ,  Sang-Woo Whangbo ,  Min-Seok Oh ,  Hye-Young Ryu ,  Hong-Kee Chin

IPC分类号： H01L21/00

CPC分类号： H01L27/124 ,  G02F2001/13629 ,  H01L29/458

摘要： The present invention provides a manufacturing method of a thin film transistor array panel, which includes forming a gate line on a substrate; forming a gate insulating layer, a semiconductor layer, and an ohmic contact on the gate line; forming a first conducting film including Mo, a second conducting film including Al, and a third conducting film including Mo on the ohmic contact; forming a first photoresist pattern on the third conducting film; etching the first, second, and third conducting films, the ohmic contact, and the semiconductor layer using the first photoresist pattern as a mask; removing the first photoresist pattern by a predetermined thickness to form a second photoresist pattern; etching the first, second, and third conducting films using the second photoresist pattern as a mask to expose a portion of the ohmic contact; and etching the exposed ohmic contact using a Cl-containing gas and a F-containing gas.

摘要翻译： 本发明提供一种薄膜晶体管阵列面板的制造方法，其包括在基板上形成栅极线; 在栅极线上形成栅极绝缘层，半导体层和欧姆接触; 形成包括Mo的第一导电膜，包括Al的第二导电膜和在欧姆接触上包含Mo的第三导电膜; 在所述第三导电膜上形成第一光致抗蚀剂图案; 使用第一光致抗蚀剂图案作为掩模蚀刻第一，第二和第三导电膜，欧姆接触和半导体层; 将第一光致抗蚀剂图案去除预定厚度以形成第二光致抗蚀剂图案; 使用第二光致抗蚀剂图案作为掩模蚀刻第一，第二和第三导电膜以暴露欧姆接触的一部分; 并使用含Cl气体和含F气体蚀刻暴露的欧姆接触。

公开(公告)号：US20070012967A1

公开(公告)日：2007-01-18

申请号：US11486330

申请日：2006-07-12

申请人： Sang-Gab Kim ,  Woo-Geun Lee ,  Shi-Yul Kim ,  Jin-Ho Ju ,  Jang-Soo Kim ,  Sang-Woo Whangbo ,  Min-Seok Oh ,  Hye-Young Ryu ,  Hong-Kee Chin

发明人： Sang-Gab Kim ,  Woo-Geun Lee ,  Shi-Yul Kim ,  Jin-Ho Ju ,  Jang-Soo Kim ,  Sang-Woo Whangbo ,  Min-Seok Oh ,  Hye-Young Ryu ,  Hong-Kee Chin

IPC分类号： H01L31/113

CPC分类号： H01L27/124 ,  G02F2001/13629 ,  H01L29/458

摘要： The present invention provides a manufacturing method of a thin film transistor array panel, which includes forming a gate line on a substrate; forming a gate insulating layer, a semiconductor layer, and an ohmic contact on the gate line; forming a first conducting film including Mo, a second conducting film including Al, and a third conducting film including Mo on the ohmic contact; forming a first photoresist pattern on the third conducting film; etching the first, second, and third conducting films, the ohmic contact, and the semiconductor layer using the first photoresist pattern as a mask; removing the first photoresist pattern by a predetermined thickness to form a second photoresist pattern; etching the first, second, and third conducting films using the second photoresist pattern as a mask to expose a portion of the ohmic contact; and etching the exposed ohmic contact using a Cl-containing gas and a F-containing gas.

摘要翻译： 本发明提供一种薄膜晶体管阵列面板的制造方法，其包括在基板上形成栅极线; 在栅极线上形成栅极绝缘层，半导体层和欧姆接触; 形成包括Mo的第一导电膜，包括Al的第二导电膜和在欧姆接触上包含Mo的第三导电膜; 在所述第三导电膜上形成第一光致抗蚀剂图案; 使用第一光致抗蚀剂图案作为掩模蚀刻第一，第二和第三导电膜，欧姆接触和半导体层; 将第一光致抗蚀剂图案去除预定厚度以形成第二光致抗蚀剂图案; 使用第二光致抗蚀剂图案作为掩模蚀刻第一，第二和第三导电膜以暴露欧姆接触的一部分; 并使用含Cl气体和含F气体蚀刻暴露的欧姆接触。

公开(公告)号：US08173493B2

公开(公告)日：2012-05-08

申请号：US12765698

申请日：2010-04-22

申请人： Sang-Gab Kim ,  Woo-Geun Lee ,  Shi-Yul Kim ,  Jin-Ho Ju ,  Jang-Soo Kim ,  Sang-Woo Whangbo ,  Min-Seok Oh ,  Hye-Young Ryu ,  Hong-Kee Chin

发明人： Sang-Gab Kim ,  Woo-Geun Lee ,  Shi-Yul Kim ,  Jin-Ho Ju ,  Jang-Soo Kim ,  Sang-Woo Whangbo ,  Min-Seok Oh ,  Hye-Young Ryu ,  Hong-Kee Chin

IPC分类号： H01L21/00 ,  H01L21/84

CPC分类号： H01L27/124 ,  G02F2001/13629 ,  H01L29/458

摘要： The present invention provides a manufacturing method of a thin film transistor array panel, which includes forming a gate line on a substrate; forming a gate insulating layer, a semiconductor layer, and an ohmic contact on the gate line; forming a first conducting film including Mo, a second conducting film including Al, and a third conducting film including Mo on the ohmic contact; forming a first photoresist pattern on the third conducting film; etching the first, second, and third conducting films, the ohmic contact, and the semiconductor layer using the first photoresist pattern as a mask; removing the first photoresist pattern by a predetermined thickness to form a second photoresist pattern; etching the first, second, and third conducting films using the second photoresist pattern as a mask to expose a portion of the ohmic contact; and etching the exposed ohmic contact using a Cl-containing gas and a F-containing gas.

摘要翻译： 本发明提供一种薄膜晶体管阵列面板的制造方法，其包括在基板上形成栅极线; 在栅极线上形成栅极绝缘层，半导体层和欧姆接触; 形成包括Mo的第一导电膜，包括Al的第二导电膜和在欧姆接触上包含Mo的第三导电膜; 在所述第三导电膜上形成第一光致抗蚀剂图案; 使用第一光致抗蚀剂图案作为掩模蚀刻第一，第二和第三导电膜，欧姆接触和半导体层; 将第一光致抗蚀剂图案去除预定厚度以形成第二光致抗蚀剂图案; 使用第二光致抗蚀剂图案作为掩模蚀刻第一，第二和第三导电膜以暴露欧姆接触的一部分; 并使用含Cl气体和含F气体蚀刻暴露的欧姆接触。

公开(公告)号：US20100203715A1

公开(公告)日：2010-08-12

申请号：US12765698

申请日：2010-04-22

申请人： Sang-Gab KIM ,  Woo-Geun Lee ,  Shi-Yul Kim ,  Jin-Ho Ju ,  Jang-Soo Kim ,  Sang-Woo Whangbo ,  Min-Seok Oh ,  Hye-Young Ryu ,  Hong-Kee Chin

发明人： Sang-Gab KIM ,  Woo-Geun Lee ,  Shi-Yul Kim ,  Jin-Ho Ju ,  Jang-Soo Kim ,  Sang-Woo Whangbo ,  Min-Seok Oh ,  Hye-Young Ryu ,  Hong-Kee Chin

IPC分类号： H01L21/28

CPC分类号： H01L27/124 ,  G02F2001/13629 ,  H01L29/458

摘要： The present invention provides a manufacturing method of a thin film transistor array panel, which includes forming a gate line on a substrate; forming a gate insulating layer, a semiconductor layer, and an ohmic contact on the gate line; forming a first conducting film including Mo, a second conducting film including Al, and a third conducting film including Mo on the ohmic contact; forming a first photoresist pattern on the third conducting film; etching the first, second, and third conducting films, the ohmic contact, and the semiconductor layer using the first photoresist pattern as a mask; removing the first photoresist pattern by a predetermined thickness to form a second photoresist pattern; etching the first, second, and third conducting films using the second photoresist pattern as a mask to expose a portion of the ohmic contact; and etching the exposed ohmic contact using a Cl-containing gas and a F-containing gas.

摘要翻译： 本发明提供一种薄膜晶体管阵列面板的制造方法，其包括在基板上形成栅极线; 在栅极线上形成栅极绝缘层，半导体层和欧姆接触; 形成包括Mo的第一导电膜，包括Al的第二导电膜和在欧姆接触上包含Mo的第三导电膜; 在所述第三导电膜上形成第一光致抗蚀剂图案; 使用第一光致抗蚀剂图案作为掩模蚀刻第一，第二和第三导电膜，欧姆接触和半导体层; 将第一光致抗蚀剂图案去除预定厚度以形成第二光致抗蚀剂图案; 使用第二光致抗蚀剂图案作为掩模蚀刻第一，第二和第三导电膜以暴露欧姆接触的一部分; 并使用含Cl气体和含F气体蚀刻暴露的欧姆接触。

公开(公告)号：US20080203393A1

公开(公告)日：2008-08-28

申请号：US12099718

申请日：2008-04-08

申请人： Sang-Gab KIM ,  Woo-Geun Lee ,  Shi-Yul Kim ,  Jin-Ho Ju ,  Jang-Soo Kim ,  Sang-Woo Whangbo ,  Min-Seok Oh ,  Hye-Young Ryu ,  Hong-Kee Chin

发明人： Sang-Gab KIM ,  Woo-Geun Lee ,  Shi-Yul Kim ,  Jin-Ho Ju ,  Jang-Soo Kim ,  Sang-Woo Whangbo ,  Min-Seok Oh ,  Hye-Young Ryu ,  Hong-Kee Chin

IPC分类号： H01L27/088

CPC分类号： H01L27/124 ,  G02F2001/13629 ,  H01L29/458

摘要： The present invention provides a manufacturing method of a thin film transistor array panel, which includes forming a gate line on a substrate; forming a gate insulating layer, a semiconductor layer, and an ohmic contact on the gate line; forming a first conducting film including Mo, a second conducting film including Al, and a third conducting film including Mo on the ohmic contact; forming a first photoresist pattern on the third conducting film; etching the first, second, and third conducting films, the ohmic contact, and the semiconductor layer using the first photoresist pattern as a mask; removing the first photoresist pattern by a predetermined thickness to form a second photoresist pattern; etching the first, second, and third conducting films using the second photoresist pattern as a mask to expose a portion of the ohmic contact; and etching the exposed ohmic contact using a Cl-containing gas and a F-containing gas.

摘要翻译： 本发明提供一种薄膜晶体管阵列面板的制造方法，其包括在基板上形成栅极线; 在栅极线上形成栅极绝缘层，半导体层和欧姆接触; 形成包括Mo的第一导电膜，包括Al的第二导电膜和在欧姆接触上包含Mo的第三导电膜; 在所述第三导电膜上形成第一光致抗蚀剂图案; 使用第一光致抗蚀剂图案作为掩模蚀刻第一，第二和第三导电膜，欧姆接触和半导体层; 将第一光致抗蚀剂图案去除预定厚度以形成第二光致抗蚀剂图案; 使用第二光致抗蚀剂图案作为掩模蚀刻第一，第二和第三导电膜以暴露欧姆接触的一部分; 并使用含Cl气体和含F气体蚀刻暴露的欧姆接触。

公开(公告)号：US20060131581A1

公开(公告)日：2006-06-22

申请号：US11255801

申请日：2005-10-21

申请人： Sang-Gab Kim ,  Min-Seok Oh ,  Hong-Kee Chin ,  Jeong-Min Park ,  Shi-Yul Kim ,  Hee-Hwan Choe

发明人： Sang-Gab Kim ,  Min-Seok Oh ,  Hong-Kee Chin ,  Jeong-Min Park ,  Shi-Yul Kim ,  Hee-Hwan Choe

IPC分类号： H01L29/04

CPC分类号： H01L29/458 ,  G02F2001/136236 ,  H01L27/124 ,  H01L27/1288

摘要： A method for manufacturing a TFT array panel including forming a gate line having a gate electrode on a insulating layer, a gate insulating layer on the gate line, a semiconductor on the gate insulating layer, an ohmic contact on the semiconductor, a data line having a source electrode and a drain electrode apart form the source electrode on the ohmic contact, a passivation layer having a contact hole to expose the drain electrode, and a pixel electrode connected to the drain electrode through the contact hole. The drain electrode and the source electrode are formed by a photolithography using a negative photoresist pattern. The negative photoresist pattern includes a first portion having a first thickness corresponding to a channel area, a second portion having a second thickness corresponding to a data line area, and a third portion having a third thickness corresponding to another area.

摘要翻译： 一种TFT阵列板的制造方法，包括在绝缘层上形成具有栅电极的栅极线，栅极线上的栅极绝缘层，栅极绝缘层上的半导体，半导体上的欧姆接触，数据线， 源电极和漏电极分开形成欧姆接触上的源电极，具有露出漏电极的接触孔的钝化层和通过接触孔连接到漏电极的像素电极。 漏电极和源电极通过使用负光致抗蚀剂图案的光刻形成。 负型光致抗蚀剂图案包括具有对应于沟道区域的第一厚度的第一部分，具有对应于数据线区域的第二厚度的第二部分和具有对应于另一区域的第三厚度的第三部分。

公开(公告)号：US07688417B2

公开(公告)日：2010-03-30

申请号：US11255801

申请日：2005-10-21

申请人： Sang-Gab Kim ,  Min-Seok Oh ,  Hong-Kee Chin ,  Jeong-Min Park ,  Shi-Yul Kim ,  Hee-Hwan Choe

发明人： Sang-Gab Kim ,  Min-Seok Oh ,  Hong-Kee Chin ,  Jeong-Min Park ,  Shi-Yul Kim ,  Hee-Hwan Choe

IPC分类号： G02F1/1333 ,  G02F1/133 ,  G02F1/13

CPC分类号： H01L29/458 ,  G02F2001/136236 ,  H01L27/124 ,  H01L27/1288

摘要： A method for manufacturing a TFT array panel including forming a gate line having a gate electrode on a insulating layer, a gate insulating layer on the gate line, a semiconductor on the gate insulating layer, an ohmic contact on the semiconductor, a data line having a source electrode and a drain electrode apart form the source electrode on the ohmic contact, a passivation layer having a contact hole to expose the drain electrode, and a pixel electrode connected to the drain electrode through the contact hole. The drain electrode and the source electrode are formed by a photolithography using a negative photoresist pattern. The negative photoresist pattern includes a first portion having a first thickness corresponding to a channel area, a second portion having a second thickness corresponding to a data line area, and a third portion having a third thickness corresponding to another area.

摘要翻译： 一种TFT阵列板的制造方法，包括在绝缘层上形成具有栅电极的栅极线，栅极线上的栅极绝缘层，栅极绝缘层上的半导体，半导体上的欧姆接触，数据线， 源电极和漏电极分开形成欧姆接触上的源电极，具有露出漏电极的接触孔的钝化层和通过接触孔连接到漏电极的像素电极。 漏电极和源电极通过使用负光致抗蚀剂图案的光刻形成。 负型光致抗蚀剂图案包括具有对应于沟道区域的第一厚度的第一部分，具有对应于数据线区域的第二厚度的第二部分和具有对应于另一区域的第三厚度的第三部分。