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    Fused multiply-add apparatus and method
    1.
    发明授权
    Fused multiply-add apparatus and method 有权
    熔融多重加法装置及方法

    公开(公告)号：US08805915B2

    公开(公告)日：2014-08-12

    申请号：US13153885

    申请日：2011-06-06

    申请人： Hyeong-Seok Yu ,  Dong-Kwan Suh ,  Suk-Jin Kim ,  San Kim ,  Yong-Surk Lee

    发明人： Hyeong-Seok Yu ,  Dong-Kwan Suh ,  Suk-Jin Kim ,  San Kim ,  Yong-Surk Lee

    IPC分类号： G06F7/38

    CPC分类号： G06F7/483 ,  G06F7/5443

    摘要： A fixed multiply-add (FMA) apparatus and method are provided. The FMA apparatus includes a partial product generator configured to generate a partial sum and a partial carry, a carry save adder configured to generate a partial sum having a first bit size and a partial carry having the first bit size by adding the partial sum and the partial carry to least significant bits (LSBs) of the mantissa of a third floating-point number, a carry select adder configured to generate a mantissa having a second bit size by adding the first bit-size partial sum and the first bit-size partial carry to most significant bits (MSBs) of the third floating-point number, and a selector configured to transmit the first bit-size partial sum and the first bit-size partial carry to the carry save adder or the carry select adder according to whether the mantissa of the third floating-point number is zero.

    摘要翻译： 提供固定的乘法（FMA）装置和方法。 该FMA装置包括：部分乘积发生器，被配置为产生部分和和部分进位;进位保存加法器，被配置为通过将部分和和相加来产生具有第一位大小的部分和和具有第一位大小的部分进位 部分进位到第三浮点数的尾数的最低有效位（LSB），进位选择加法器，被配置为通过将第一位大小部分和和第一位大小部分相加来生成具有第二位大小的尾数 携带到第三浮点数的最高有效位（MSB），以及选择器，被配置为根据是否将第一位大小部分和和第一位大小部分进位发送到进位存储加法器或进位选择加法器 第三个浮点数的尾数为零。

    FUSED MULTIPLY-ADD APPARATUS AND METHOD
    2.
    发明申请
    FUSED MULTIPLY-ADD APPARATUS AND METHOD 有权
    熔融多媒体设备和方法

    公开(公告)号：US20120124117A1

    公开(公告)日：2012-05-17

    申请号：US13153885

    申请日：2011-06-06

    申请人： Hyeong-Seok Yu ,  Dong-Kwan Suh ,  Suk-Jin Kim ,  San Kim ,  Yong-Surk Lee

    发明人： Hyeong-Seok Yu ,  Dong-Kwan Suh ,  Suk-Jin Kim ,  San Kim ,  Yong-Surk Lee

    IPC分类号： G06F7/487 ,  G06F7/485 ,  G06F5/01

    CPC分类号： G06F7/483 ,  G06F7/5443

    摘要： A fixed multiply-add (FMA) apparatus and method are provided. The FMA apparatus includes a partial product generator configured to generate a partial sum and a partial carry, a carry save adder configured to generate a partial sum having a first bit size and a partial carry having the first bit size by adding the partial sum and the partial carry to least significant bits (LSBs) of the mantissa of a third floating-point number, a carry select adder configured to generate a mantissa having a second bit size by adding the first bit-size partial sum and the first bit-size partial carry to most significant bits (MSBs) of the third floating-point number, and a selector configured to transmit the first bit-size partial sum and the first bit-size partial carry to the carry save adder or the carry select adder according to whether the mantissa of the third floating-point number is zero.

    摘要翻译： 提供固定的乘法（FMA）装置和方法。 该FMA装置包括：部分乘积发生器，被配置为产生部分和和部分进位;进位保存加法器，被配置为通过将部分和和相加来产生具有第一位大小的部分和和具有第一位大小的部分进位 部分进位到第三浮点数的尾数的最低有效位（LSB），进位选择加法器，被配置为通过将第一位大小部分和和第一位大小部分相加来生成具有第二位大小的尾数 携带到第三浮点数的最高有效位（MSB），以及选择器，被配置为根据是否将第一位大小部分和和第一位大小部分进位发送到进位存储加法器或进位选择加法器 第三个浮点数的尾数为零。

    RECONFIGURABLE PROCESSOR AND MINI-CORE OF RECONFIGURABLE PROCESSOR
    3.
    发明申请
    RECONFIGURABLE PROCESSOR AND MINI-CORE OF RECONFIGURABLE PROCESSOR 有权
    可重构处理器和可重构处理器的微型核心

    公开(公告)号：US20130151815A1

    公开(公告)日：2013-06-13

    申请号：US13711418

    申请日：2012-12-11

    申请人： Dong-Kwan Suh ,  Suk-Jin Kim ,  Hyeong-Seok Yu ,  Ki-Seok Kwon ,  Jae-Un Park

    发明人： Dong-Kwan Suh ,  Suk-Jin Kim ,  Hyeong-Seok Yu ,  Ki-Seok Kwon ,  Jae-Un Park

    IPC分类号： G06F15/78

    CPC分类号： G06F15/7867 ,  G06F9/3001 ,  G06F9/3867

    摘要： A reconfigurable processor includes a plurality of mini-cores and an external network to which the mini-cores are connected. Each of the mini-cores includes a first function unit including a first group of operation elements, a second function unit including a second group of operation elements that is different from the first group of operation elements, and an internal network to which the first function unit and the second function unit are connected.

    摘要翻译： 可重配置处理器包括多个微型核心和连接微型核心的外部网络。 每个微型核心包括包括第一组操作元件的第一功能单元，包括与第一组操作元件不同的第二组操作元件的第二功能单元，以及内部网络，第一功能单元 单元和第二个功能单元连接。

    RECONFIGURABLE PROCESSOR AND RECONFIGURABLE PROCESSING METHOD
    4.
    发明申请
    RECONFIGURABLE PROCESSOR AND RECONFIGURABLE PROCESSING METHOD 有权
    可重构处理器和可重构处理方法

    公开(公告)号：US20110219207A1

    公开(公告)日：2011-09-08

    申请号：US12987391

    申请日：2011-01-10

    申请人： Dong-Kwan Suh ,  Hyeong-Seok Yu ,  Suk-Jin Kim

    发明人： Dong-Kwan Suh ,  Hyeong-Seok Yu ,  Suk-Jin Kim

    IPC分类号： G06F15/76 ,  G06F9/22

    CPC分类号： G06F9/22 ,  G06F15/76 ,  G06F15/7867

    摘要： A reconfigurable processor for efficiently performing a vector operation, and a method of controlling the reconfigurable processor are provided. The reconfigurable processor designates at least one of a plurality of processing elements as a vector lane based on vector lane configuration information, and allocates a vector operation to the designated vector lane.

    摘要翻译： 提供了一种用于有效执行向量操作的可重构处理器，以及一种控制可重构处理器的方法。 可重配置处理器基于向量车道配​​置信息将多个处理元件中的至少一个指定为向量车道，并且向指定的向量车道分配向量操作。

    Apparatus and method for converting data between a floating-point number and an integer
    6.
    发明授权
    Apparatus and method for converting data between a floating-point number and an integer 有权
    用于在浮点数和整数之间转换数据的装置和方法

    公开(公告)号：US08874630B2

    公开(公告)日：2014-10-28

    申请号：US13101356

    申请日：2011-05-05

    申请人： Hyeong-Seok Yu ,  Suk-Jin Kim ,  Sang-Su Park ,  Yong-Surk Lee

    发明人： Hyeong-Seok Yu ,  Suk-Jin Kim ,  Sang-Su Park ,  Yong-Surk Lee

    IPC分类号： G06F7/00 ,  G06F7/483 ,  H03M7/24

    CPC分类号： G06F7/483 ,  H03M7/24

    摘要： An apparatus and method for converting data between a floating-point number and an integer is provided. The apparatus includes a data converter configured to determine a sign of input binary data and an output format to which to convert the input binary data and convert the input binary data into a one's complement number based on the sign and the output format of the input binary data, a bias value generator configured to determine whether the input binary data has been rounded up based on a rounding mode of the input binary data and generate a bias value accordingly; and an adder configured to convert the input binary data into a two's complement number by adding the one's complement number and the bias value.

    摘要翻译： 提供了一种用于在浮点数和整数之间转换数据的装置和方法。 该装置包括：数据转换器，被配置为基于输入二进制数据的符号和输出格式确定输入二进制数据的符号和输出格式，转换输入的二进制数据并将输入的二进制数据转换为补码 数据，偏置值发生器，被配置为基于输入二进制数据的舍入模式来确定输入的二进制数据是否已被舍入，并相应地生成偏差值; 以及加法器，被配置为通过将所述补码和偏置值相加来将输入的二进制数据转换成二进制补码。

    METHOD AND APPARATUS FOR CALCULATING THE NUMBER OF LEADING ZERO BITS OF A BINARY OPERATION
    7.
    发明申请
    METHOD AND APPARATUS FOR CALCULATING THE NUMBER OF LEADING ZERO BITS OF A BINARY OPERATION 有权
    用于计算二进制操作的领先零位数的方法和装置

    公开(公告)号：US20120203811A1

    公开(公告)日：2012-08-09

    申请号：US13171536

    申请日：2011-06-29

    申请人： Hyeong-Seok Yu

    发明人： Hyeong-Seok Yu

    IPC分类号： G06F7/02

    CPC分类号： G06F7/74 ,  G06F7/485 ,  G06F7/50

    摘要： Provided are an apparatus and method for calculating the number of leading zero bits of a binary operation. The apparatus and method may accurately predict the number of leading zero bits using a binary tree structure of an input operand for a binary operation and reduce operation delay time due to the increase in number of bits of the operand. The method may include generating 2n first functions by performing a logical operation on two input binary numbers on a bit-by-bit basis, calculating a second function by combining the first functions and a leading zero bit candidate value of the second function, and determining a final number of leading zero bits by recursively performing the calculating

    摘要翻译： 提供了一种用于计算二进制操作的前导零比特数的装置和方法。 该装置和方法可以使用用于二进制操作的输入操作数的二叉树结构来精确地预测前导零比特的数量，并且由于操作数的比特数的增加而减少操作延迟时间。 该方法可以包括通过在逐位的基础上对两个输入二进制数执行逻辑运算来产生2n个第一函数，通过组合第一函数和第二函数的前导零比特候选值来计算第二函数，以及确定 通过递归执行计算的最终数量的前导零比特

    Method for self-calibration in a mobile receiver
    8.
    发明申请
    Method for self-calibration in a mobile receiver 审中-公开
    移动接收机中的自校准方法

    公开(公告)号：US20070211808A1

    公开(公告)日：2007-09-13

    申请号：US11709910

    申请日：2007-02-22

    申请人： Hyun-Il Kang ,  Jae-Kon Lee ,  Hyeong-Seok Yu ,  Sang-Hyun Woo

    发明人： Hyun-Il Kang ,  Jae-Kon Lee ,  Hyeong-Seok Yu ,  Sang-Hyun Woo

    IPC分类号： H04K1/10

    CPC分类号： H04L27/2647 ,  H04B17/0085 ,  H04B17/21 ,  H04L2027/0016 ,  H04L2027/0024

    摘要： Provided is an apparatus and method for calibrating an imbalance characteristic of a received signal of a frequency domain in a mobile receiver which supports an Orthogonal Frequency Division Multiplexing (OFDM) scheme. To this end, a received signal of a radio frequency band is converted into a baseband signal by using a carrier, and the baseband received signal is converted from a time domain signal to a frequency domain signal. Then, a calibration coefficient is measured by using two consecutively received signals from the Fast Fourier Transform (FFT) unit. An imbalance component included in the received signal of the frequency domain due to an imbalance of the carrier is removed by using the measured calibration coefficient. In this case, the two consecutively received signals refer to two transmission signals consecutively transmitted from a transmitter, and the two transmission signals are predetermined signals.

    摘要翻译： 提供了一种用于校准支持正交频分复用（OFDM）方案的移动接收机中的频域的接收信号的不平衡特性的装置和方法。 为此，通过使用载波将无线电频带的接收信号转换为基带信号，并将基带接收信号从时域信号转换为频域信号。 然后，通过使用来自快速傅里叶变换（FFT）单元的两个连续接收的信号来测量校准系数。 通过使用测量的校准系数来消除由于载波的不平衡而包括在频域的接收信号中的不平衡分量。 在这种情况下，两个连续接收的信号是指从发送机连续发送的两个发送信号，两个发送信号是预定信号。

    Apparatus and method for generating partial product for polynomial operation
    10.
    发明授权
    Apparatus and method for generating partial product for polynomial operation 有权
    用于生成用于多项式运算的部分乘积的装置和方法

    公开(公告)号：US09354843B2

    公开(公告)日：2016-05-31

    申请号：US13588250

    申请日：2012-08-17

    申请人： Hyeong-Seok Yu

    发明人： Hyeong-Seok Yu

    IPC分类号： G06F7/533

    CPC分类号： G06F7/5338

    摘要： An apparatus and a method for generating a partial product for a polynomial operation are provided. The apparatus includes first encoders, each of the first encoders configured to selectively generate and output one of mutually exclusive values based on two inputs. The apparatus further includes a second encoder configured to generate and output two candidate partial products based on an output from a first one of the first encoders that is provided at a reference bit position of the inputs, an output from a second one of the first encoders that is provided at an upper bit position of the inputs, and a multiplicand. The apparatus further includes a multiplexer configured to select one of the candidate partial products output from the second encoder.

    摘要翻译： 提供了一种用于产生用于多项式操作的部分乘积的装置和方法。 该设备包括第一编码器，每个第一编码器被配置为基于两个输入选择性地生成和输出互斥值中的一个。 该装置还包括第二编码器，其被配置为基于来自提供在输入的参考位位置处的第一编码器中的第一编码器的输出来产生和输出两个候选部分乘积，来自第一编码器中的第二编码器的输出 被提供在输入的高位位置，被乘数。 该装置还包括多路复用器，其被配置为选择从第二编码器输出的候选部分乘积之一。