公开(公告)号：US09354843B2

公开(公告)日：2016-05-31

申请号：US13588250

申请日：2012-08-17

Applicant: Hyeong-Seok Yu

Inventor： Hyeong-Seok Yu

IPC: G06F7/533

CPC classification number: G06F7/5338

Abstract: An apparatus and a method for generating a partial product for a polynomial operation are provided. The apparatus includes first encoders, each of the first encoders configured to selectively generate and output one of mutually exclusive values based on two inputs. The apparatus further includes a second encoder configured to generate and output two candidate partial products based on an output from a first one of the first encoders that is provided at a reference bit position of the inputs, an output from a second one of the first encoders that is provided at an upper bit position of the inputs, and a multiplicand. The apparatus further includes a multiplexer configured to select one of the candidate partial products output from the second encoder.

Abstract translation: 提供了一种用于产生用于多项式操作的部分乘积的装置和方法。 该设备包括第一编码器，每个第一编码器被配置为基于两个输入选择性地生成和输出互斥值中的一个。 该装置还包括第二编码器，其被配置为基于来自提供在输入的参考位位置处的第一编码器中的第一编码器的输出来产生和输出两个候选部分乘积，来自第一编码器中的第二编码器的输出 被提供在输入的高位位置，被乘数。 该装置还包括多路复用器，其被配置为选择从第二编码器输出的候选部分乘积之一。

公开(公告)号：US09135003B2

公开(公告)日：2015-09-15

申请号：US12987391

申请日：2011-01-10

Applicant: Dong-Kwan Suh ,  Hyeong-Seok Yu ,  Suk-Jin Kim

Inventor： Dong-Kwan Suh ,  Hyeong-Seok Yu ,  Suk-Jin Kim

IPC: G06F9/44 ,  G06F9/22 ,  G06F15/78 ,  G06F15/76

CPC classification number: G06F9/22 ,  G06F15/76 ,  G06F15/7867

Abstract: A reconfigurable processor for efficiently performing a vector operation, and a method of controlling the reconfigurable processor are provided. The reconfigurable processor designates at least one of a plurality of processing elements as a vector lane based on vector lane configuration information, and allocates a vector operation to the designated vector lane.

Abstract translation: 提供了一种用于有效执行向量操作的可重构处理器，以及一种控制可重构处理器的方法。 可重配置处理器基于向量车道配​​置信息将多个处理元件中的至少一个指定为向量车道，并且向指定的向量车道分配向量操作。

公开(公告)号：US20120124117A1

公开(公告)日：2012-05-17

申请号：US13153885

申请日：2011-06-06

Applicant: Hyeong-Seok Yu ,  Dong-Kwan Suh ,  Suk-Jin Kim ,  San Kim ,  Yong-Surk Lee

Inventor： Hyeong-Seok Yu ,  Dong-Kwan Suh ,  Suk-Jin Kim ,  San Kim ,  Yong-Surk Lee

IPC: G06F7/487 ,  G06F7/485 ,  G06F5/01

CPC classification number: G06F7/483 ,  G06F7/5443

Abstract: A fixed multiply-add (FMA) apparatus and method are provided. The FMA apparatus includes a partial product generator configured to generate a partial sum and a partial carry, a carry save adder configured to generate a partial sum having a first bit size and a partial carry having the first bit size by adding the partial sum and the partial carry to least significant bits (LSBs) of the mantissa of a third floating-point number, a carry select adder configured to generate a mantissa having a second bit size by adding the first bit-size partial sum and the first bit-size partial carry to most significant bits (MSBs) of the third floating-point number, and a selector configured to transmit the first bit-size partial sum and the first bit-size partial carry to the carry save adder or the carry select adder according to whether the mantissa of the third floating-point number is zero.

Abstract translation: 提供固定的乘法（FMA）装置和方法。 该FMA装置包括：部分乘积发生器，被配置为产生部分和和部分进位;进位保存加法器，被配置为通过将部分和和相加来产生具有第一位大小的部分和和具有第一位大小的部分进位 部分进位到第三浮点数的尾数的最低有效位（LSB），进位选择加法器，被配置为通过将第一位大小部分和和第一位大小部分相加来生成具有第二位大小的尾数 携带到第三浮点数的最高有效位（MSB），以及选择器，被配置为根据是否将第一位大小部分和和第一位大小部分进位发送到进位存储加法器或进位选择加法器 第三个浮点数的尾数为零。

公开(公告)号：US20070159162A1

公开(公告)日：2007-07-12

申请号：US11636083

申请日：2006-12-08

Applicant: Hyun-Il Kang ,  Jae-Kon Lee ,  Young-Hwan Lee ,  Hyeong-Seok Yu ,  Sang-Hyun Woo

Inventor： Hyun-Il Kang ,  Jae-Kon Lee ,  Young-Hwan Lee ,  Hyeong-Seok Yu ,  Sang-Hyun Woo

IPC: G01R31/28

CPC classification number: H04B17/0085 ,  H04B17/21

Abstract: Disclosed is a method and an apparatus for self-calibrating a Direct Current (DC) offset and an imbalance between orthogonal signals, which may occur in a mobile transceiver. In the apparatus, a transmitter of a mobile terminal functions as a signal generator, and a receiver of the mobile terminal functions as a response characteristic detector. Further, a baseband processor applies test signals to the transmitter, receives the test signals returning from the receiver, and compensates the imbalance and DC offset for the transmitter side and the receiver side by using the test signals. The test signal is applied to only one of the I channel path and the Q channel path, and an RF band signal output from the transmission side by the test signal is used as an input signal to the reception side.

Abstract translation: 公开了用于自校准直流（DC）偏移和正交信号之间的不平衡的方法和装置，其可能发生在移动收发器中。 在该装置中，移动终端的发射机用作信号发生器，移动终端的接收机用作响应特性检测器。 此外，基带处理器将测试信号施加到发射机，接收从接收机返回的测试信号，并且通过使用测试信号来补偿发射机侧和接收机侧的不平衡和DC偏移。 测试信号仅施加到I信道路径和Q信道路径中的一个，并且通过测试信号从发送侧输出的RF频带信号被用作到接收侧的输入信号。

公开(公告)号：US08874630B2

公开(公告)日：2014-10-28

申请号：US13101356

申请日：2011-05-05

Applicant: Hyeong-Seok Yu ,  Suk-Jin Kim ,  Sang-Su Park ,  Yong-Surk Lee

Inventor： Hyeong-Seok Yu ,  Suk-Jin Kim ,  Sang-Su Park ,  Yong-Surk Lee

IPC: G06F7/00 ,  G06F7/483 ,  H03M7/24

CPC classification number: G06F7/483 ,  H03M7/24

Abstract: An apparatus and method for converting data between a floating-point number and an integer is provided. The apparatus includes a data converter configured to determine a sign of input binary data and an output format to which to convert the input binary data and convert the input binary data into a one's complement number based on the sign and the output format of the input binary data, a bias value generator configured to determine whether the input binary data has been rounded up based on a rounding mode of the input binary data and generate a bias value accordingly; and an adder configured to convert the input binary data into a two's complement number by adding the one's complement number and the bias value.

Abstract translation: 提供了一种用于在浮点数和整数之间转换数据的装置和方法。 该装置包括：数据转换器，被配置为基于输入二进制数据的符号和输出格式确定输入二进制数据的符号和输出格式，转换输入的二进制数据并将输入的二进制数据转换为补码 数据，偏置值发生器，被配置为基于输入二进制数据的舍入模式来确定输入的二进制数据是否已被舍入，并相应地生成偏差值; 以及加法器，被配置为通过将所述补码和偏置值相加来将输入的二进制数据转换成二进制补码。

公开(公告)号：US08805904B2

公开(公告)日：2014-08-12

申请号：US13171536

申请日：2011-06-29

Applicant: Hyeong-Seok Yu

Inventor： Hyeong-Seok Yu

IPC: G06F7/00

CPC classification number: G06F7/74 ,  G06F7/485 ,  G06F7/50

Abstract: Provided are an apparatus and method for calculating the number of leading zero bits of a binary operation. The apparatus and method may accurately predict the number of leading zero bits using a binary tree structure of an input operand for a binary operation and reduce operation delay time due to the increase in number of bits of the operand. The method may include generating 2n first functions by performing a logical operation on two input binary numbers on a bit-by-bit basis, calculating a second function by combining the first functions and a leading zero bit candidate value of the second function, and determining a final number of leading zero bits by recursively performing the calculating.

Abstract translation: 提供了一种用于计算二进制操作的前导零比特数的装置和方法。 该装置和方法可以使用用于二进制操作的输入操作数的二叉树结构来精确地预测前导零比特的数量，并且由于操作数的比特数的增加而减少操作延迟时间。 该方法可以包括通过在逐位的基础上对两个输入二进制数执行逻辑运算来产生2n个第一函数，通过组合第一函数和第二函数的前导零比特候选值来计算第二函数，以及确定 通过递归执行计算的最终数量的前导零比特。

公开(公告)号：US20110219207A1

公开(公告)日：2011-09-08

申请号：US12987391

申请日：2011-01-10

Applicant: Dong-Kwan Suh ,  Hyeong-Seok Yu ,  Suk-Jin Kim

Inventor： Dong-Kwan Suh ,  Hyeong-Seok Yu ,  Suk-Jin Kim

IPC: G06F15/76 ,  G06F9/22

CPC classification number: G06F9/22 ,  G06F15/76 ,  G06F15/7867

Abstract: A reconfigurable processor for efficiently performing a vector operation, and a method of controlling the reconfigurable processor are provided. The reconfigurable processor designates at least one of a plurality of processing elements as a vector lane based on vector lane configuration information, and allocates a vector operation to the designated vector lane.

Abstract translation: 提供了一种用于有效执行向量操作的可重构处理器，以及一种控制可重构处理器的方法。 可重配置处理器基于向量车道配​​置信息将多个处理元件中的至少一个指定为向量车道，并且向指定的向量车道分配向量操作。

公开(公告)号：US20070214203A1

公开(公告)日：2007-09-13

申请号：US11707618

申请日：2007-02-16

Applicant: Hyeong-Seok Yu ,  Jae-Kon Lee ,  Chang-Woo Seo ,  Hyun-Il Kang

Inventor： Hyeong-Seok Yu ,  Jae-Kon Lee ,  Chang-Woo Seo ,  Hyun-Il Kang

IPC: G06F17/14

CPC classification number: G06F7/535 ,  G06F7/5446

Abstract: A dividing apparatus and method using coordinate rotation is disclosed. To this end, a plurality of rotation stages are sequentially performed until a divisor reaches a criterion and a rotation direction used in each of the plurality of stages is output. A division result acquired by performing rotation with respect to a dividend using the rotation direction for each of the plurality of stages is output.

Abstract translation: 公开了一种使用坐标旋转的分割装置和方法。 为此，顺序执行多个旋转台，直到除数达到标准，并且输出在多个级中的每一个中使用的旋转方向。 输出通过使用针对多个级中的每一个的旋转方向执行关于分红的旋转获得的分割结果。

公开(公告)号：US20120203811A1

公开(公告)日：2012-08-09

申请号：US13171536

申请日：2011-06-29

Applicant: Hyeong-Seok Yu

Inventor： Hyeong-Seok Yu

IPC: G06F7/02

CPC classification number: G06F7/74 ,  G06F7/485 ,  G06F7/50

Abstract: Provided are an apparatus and method for calculating the number of leading zero bits of a binary operation. The apparatus and method may accurately predict the number of leading zero bits using a binary tree structure of an input operand for a binary operation and reduce operation delay time due to the increase in number of bits of the operand. The method may include generating 2n first functions by performing a logical operation on two input binary numbers on a bit-by-bit basis, calculating a second function by combining the first functions and a leading zero bit candidate value of the second function, and determining a final number of leading zero bits by recursively performing the calculating

Abstract translation: 提供了一种用于计算二进制操作的前导零比特数的装置和方法。 该装置和方法可以使用用于二进制操作的输入操作数的二叉树结构来精确地预测前导零比特的数量，并且由于操作数的比特数的增加而减少操作延迟时间。 该方法可以包括通过在逐位的基础上对两个输入二进制数执行逻辑运算来产生2n个第一函数，通过组合第一函数和第二函数的前导零比特候选值来计算第二函数，以及确定 通过递归执行计算的最终数量的前导零比特

公开(公告)号：US08805915B2

公开(公告)日：2014-08-12

申请号：US13153885

申请日：2011-06-06

Applicant: Hyeong-Seok Yu ,  Dong-Kwan Suh ,  Suk-Jin Kim ,  San Kim ,  Yong-Surk Lee

Inventor： Hyeong-Seok Yu ,  Dong-Kwan Suh ,  Suk-Jin Kim ,  San Kim ,  Yong-Surk Lee

IPC: G06F7/38

CPC classification number: G06F7/483 ,  G06F7/5443

Abstract: A fixed multiply-add (FMA) apparatus and method are provided. The FMA apparatus includes a partial product generator configured to generate a partial sum and a partial carry, a carry save adder configured to generate a partial sum having a first bit size and a partial carry having the first bit size by adding the partial sum and the partial carry to least significant bits (LSBs) of the mantissa of a third floating-point number, a carry select adder configured to generate a mantissa having a second bit size by adding the first bit-size partial sum and the first bit-size partial carry to most significant bits (MSBs) of the third floating-point number, and a selector configured to transmit the first bit-size partial sum and the first bit-size partial carry to the carry save adder or the carry select adder according to whether the mantissa of the third floating-point number is zero.

Abstract translation: 提供固定的乘法（FMA）装置和方法。 该FMA装置包括：部分乘积发生器，被配置为产生部分和和部分进位;进位保存加法器，被配置为通过将部分和和相加来产生具有第一位大小的部分和和具有第一位大小的部分进位 部分进位到第三浮点数的尾数的最低有效位（LSB），进位选择加法器，被配置为通过将第一位大小部分和和第一位大小部分相加来生成具有第二位大小的尾数 携带到第三浮点数的最高有效位（MSB），以及选择器，被配置为根据是否将第一位大小部分和和第一位大小部分进位发送到进位存储加法器或进位选择加法器 第三个浮点数的尾数为零。