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公开(公告)号：US08782350B2
公开(公告)日：2014-07-15
申请号：US13412243
申请日：2012-03-05
CPC分类号： G06F13/1684 , G06F13/4027 , G11C5/02 , G11C5/06 , G11C8/18 , H05K1/0216 , H05K1/0243 , H05K2201/10053 , H05K2201/10159 , H05K2201/10189
摘要： Certain embodiments described herein include a memory module having a printed circuit board including at least one connector configured to be operatively coupled to a memory controller of a computer system. The memory module further includes a plurality of memory devices on the printed circuit board and a circuit including a first set of ports operatively coupled to at least one memory device. The circuit further includes a second set of ports operatively coupled to the at least one connector. The circuit includes a switching circuit configured to selectively operatively couple one or more ports of the second set of ports to one or more ports of the first set of ports. Each port of the first set and the second set comprises a correction circuit which reduces noise in one or more signals transmitted between the first set of ports and the second set of ports.
摘要翻译： 本文描述的某些实施例包括具有印刷电路板的存储器模块，该印刷电路板包括被配置为可操作地耦合到计算机系统的存储器控制器的至少一个连接器。 存储器模块还包括印刷电路板上的多个存储器件和包括可操作地耦合到至少一个存储器件的第一组端口的电路。 电路还包括可操作地耦合到至少一个连接器的第二组端口。 电路包括切换电路，其被配置为选择性地将第二组端口的一个或多个端口耦合到第一组端口的一个或多个端口。 第一组和第二组的每个端口包括校正电路，其减少在第一组端口和第二组端口之间传输的一个或多个信号中的噪声。
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公开(公告)号：US20120250386A1
公开(公告)日：2012-10-04
申请号：US13412243
申请日：2012-03-05
IPC分类号： G11C5/02
CPC分类号： G06F13/1684 , G06F13/4027 , G11C5/02 , G11C5/06 , G11C8/18 , H05K1/0216 , H05K1/0243 , H05K2201/10053 , H05K2201/10159 , H05K2201/10189
摘要： Certain embodiments described herein include a memory module having a printed circuit board including at least one connector configured to be operatively coupled to a memory controller of a computer system. The memory module further includes a plurality of memory devices on the printed circuit board and a circuit including a first set of ports operatively coupled to at least one memory device. The circuit further includes a second set of ports operatively coupled to the at least one connector. The circuit includes a switching circuit configured to selectively operatively couple one or more ports of the second set of ports to one or more ports of the first set of ports. Each port of the first set and the second set comprises a correction circuit which reduces noise in one or more signals transmitted between the first set of ports and the second set of ports.
摘要翻译： 本文描述的某些实施例包括具有印刷电路板的存储器模块，该印刷电路板包括被配置为可操作地耦合到计算机系统的存储器控制器的至少一个连接器。 存储器模块还包括印刷电路板上的多个存储器件和包括可操作地耦合到至少一个存储器件的第一组端口的电路。 电路还包括可操作地耦合到至少一个连接器的第二组端口。 电路包括切换电路，其被配置为选择性地将第二组端口的一个或多个端口耦合到第一组端口的一个或多个端口。 第一组和第二组的每个端口包括校正电路，其减少在第一组端口和第二组端口之间传输的一个或多个信号中的噪声。
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公开(公告)号：US08154901B1
公开(公告)日：2012-04-10
申请号：US12422853
申请日：2009-04-13
IPC分类号： G11C5/02
CPC分类号： G06F13/1684 , G06F13/4027 , G11C5/02 , G11C5/06 , G11C8/18 , H05K1/0216 , H05K1/0243 , H05K2201/10053 , H05K2201/10159 , H05K2201/10189
摘要： Certain embodiments described herein include a memory module having a printed circuit board including at least one connector configured to be operatively coupled to a memory controller of a computer system. The memory module further includes a plurality of memory devices on the printed circuit board and a circuit including a first set of ports operatively coupled to at least one memory device. The circuit further includes a second set of ports operatively coupled to the at least one connector. The circuit includes a switching circuit configured to selectively operatively couple one or more ports of the second set of ports to one or more ports of the first set of ports. Each port of the first set and the second set comprises a correction circuit which reduces noise in one or more signals transmitted between the first set of ports and the second set of ports.
摘要翻译： 本文描述的某些实施例包括具有印刷电路板的存储器模块，该印刷电路板包括被配置为可操作地耦合到计算机系统的存储器控制器的至少一个连接器。 存储器模块还包括印刷电路板上的多个存储器件和包括可操作地耦合到至少一个存储器件的第一组端口的电路。 电路还包括可操作地耦合到至少一个连接器的第二组端口。 电路包括切换电路，其被配置为选择性地将第二组端口的一个或多个端口耦合到第一组端口的一个或多个端口。 第一组和第二组的每个端口包括校正电路，其减少在第一组端口和第二组端口之间传输的一个或多个信号中的噪声。
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