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公开(公告)号：US09197402B2
公开(公告)日：2015-11-24
申请号：US13997229
申请日：2012-04-10
CPC分类号： H04L7/0331 , G04F10/005 , H03L7/1974
摘要： A re-circulating time-to-digital converter (TDC) can include a triggered reference ring oscillator (TRRO) and a delay module. The triggered reference ring oscillator can, when triggered by a reference signal edge, generate a periodic ring oscillator signal with a ring oscillator period that is a selected ratio of a voltage-controlled oscillator (VCO) period. The delay module can store, in a plurality of latches, samples of a VCO signal docked by the periodic ring oscillator signal. Each latch can generate an output of the sample, and each latch output can represent a time difference polarity between VCO signal and TRRO signal. In another example, the re-circulating TDC can include the triggered reference ring oscillator, a digital frequency lock module, and a TDC post-process module. The digital frequency lock module can generate a ring oscillator control signal, which sets the ring oscillator period for the triggered reference ring oscillator. The TDC post-process module can generate a TDC output, which can be a binary representation of a phase difference between a reference signal and a VCO signal.
摘要翻译： 再循环时间 - 数字转换器（TDC）可以包括触发参考环形振荡器（TRRO）和延迟模块。 触发的参考环形振荡器可以在由参考信号边沿触发时产生周期性环形振荡器信号，其环路振荡器周期是压控振荡器（VCO）周期的选定比率。 延迟模块可以在多个锁存器中存储由周期性环形振荡器信号对接的VCO信号的采样。 每个锁存器可以产生采样的输出，并且每个锁存器输出可以表示VCO信号和TRRO信号之间的时差极性。 在另一示例中，再循环TDC可以包括触发的参考环形振荡器，数字频率锁定模块和TDC后处理模块。 数字频率锁定模块可以产生环形振荡器控制信号，为触发的参考环形振荡器设置环形振荡器周期。 TDC后处理模块可以产生TDC输出，其可以是参考信号和VCO信号之间的相位差的二进制表示。
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公开(公告)号：US20140333358A1
公开(公告)日：2014-11-13
申请号：US13997229
申请日：2012-04-10
CPC分类号： H04L7/0331 , G04F10/005 , H03L7/1974
摘要： A re-circulating time-to-digital converter (TDC) can include a triggered reference ring oscillator (TRRO) and a delay module. The triggered reference ring oscillator can, when triggered by a reference signal edge, generate a periodic ring oscillator signal with a ring oscillator period that is a selected ratio of a voltage-controlled oscillator (VCO) period. The delay module can store, in a plurality of latches, samples of a VCO signal docked by the periodic ring oscillator signal. Each latch can generate an output of the sample, and each latch output can represent a time difference polarity between VCO signal and TRRO signal. In another example, the re-circulating TDC can include the triggered reference ring oscillator, a digital frequency lock module, and a TDC post-process module. The digital frequency lock module can generate a ring oscillator control signal, which sets the ring oscillator period for the triggered reference ring oscillator. The TDC post-process module can generate a TDC output, which can be a binary representation of a phase difference between a reference signal and a VCO signal.
摘要翻译： 再循环时间 - 数字转换器（TDC）可以包括触发参考环形振荡器（TRRO）和延迟模块。 触发的参考环形振荡器可以在由参考信号边沿触发时产生周期性环形振荡器信号，其环路振荡器周期是压控振荡器（VCO）周期的选定比率。 延迟模块可以在多个锁存器中存储由周期性环形振荡器信号对接的VCO信号的采样。 每个锁存器可以产生采样的输出，并且每个锁存器输出可以表示VCO信号和TRRO信号之间的时差极性。 在另一示例中，再循环TDC可以包括触发的参考环形振荡器，数字频率锁定模块和TDC后处理模块。 数字频率锁定模块可以产生环形振荡器控制信号，为触发的参考环形振荡器设置环形振荡器周期。 TDC后处理模块可以产生TDC输出，其可以是参考信号和VCO信号之间的相位差的二进制表示。
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公开(公告)号：US20140185736A1
公开(公告)日：2014-07-03
申请号：US13997191
申请日：2011-10-01
IPC分类号： H03K21/02
CPC分类号： H03K21/023 , H03K21/026 , H03K23/542
摘要： A digital fractional frequency divider for fractionally dividing a digital frequency signal can include a plurality of clock division counter modules, a plurality of sampling modules, and a summing module. The plurality of clock division counter modules can each receive an input clock signal that is phase-shifted from a remaining plurality of input clock signals. Each clock division counter module can generate a long periodic pulse from the received input clock signal. Each sampling module can couple to an output of one of the plurality of clock division counter modules and can generate a short periodic pulse from the long periodic pulse. The summing module can sum the plurality of short periodic pulses to generate a fractional frequency clock signal.
摘要翻译： 用于分数数字频率信号的数字分数分频器可以包括多个时钟分配计数器模块，多个采样模块和求和模块。 多个时钟分配计数器模块可以各自接收从剩余的多个输入时钟信号中相移的输入时钟信号。 每个时钟分配计数器模块可以从接收到的输入时钟信号产生长周期脉冲。 每个采样模块可以耦合到多个时钟分配计数器模块之一的输出，并且可以从长周期脉冲产生短周期脉冲。 求和模块可以对多个短周期脉冲求和以产生分数频率时钟信号。
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公开(公告)号：US09013213B2
公开(公告)日：2015-04-21
申请号：US13997191
申请日：2011-10-01
CPC分类号： H03K21/023 , H03K21/026 , H03K23/542
摘要： A digital fractional frequency divider for fractionally dividing a digital frequency signal can include a plurality of clock division counter modules, a plurality of sampling modules, and a summing module. The plurality of clock division counter modules can each receive an input clock signal that is phase-shifted from a remaining plurality of input clock signals. Each clock division counter module can generate a long periodic pulse from the received input clock signal. Each sampling module can couple to an output of one of the plurality of clock division counter modules and can generate a short periodic pulse from the long periodic pulse. The summing module can sum the plurality of short periodic pulses to generate a fractional frequency clock signal.
摘要翻译： 用于分数数字频率信号的数字分数分频器可以包括多个时钟分配计数器模块，多个采样模块和求和模块。 多个时钟分配计数器模块可以各自接收从剩余的多个输入时钟信号中相移的输入时钟信号。 每个时钟分配计数器模块可以从接收到的输入时钟信号产生长周期脉冲。 每个采样模块可以耦合到多个时钟分配计数器模块之一的输出，并且可以从长周期脉冲产生短周期脉冲。 求和模块可以对多个短周期脉冲求和以产生分数频率时钟信号。
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