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    Dual gate stack CMOS structure with different dielectrics
    2.
    发明授权
    Dual gate stack CMOS structure with different dielectrics 有权
    具有不同电介质的双栅叠层CMOS结构

    公开(公告)号：US07576395B2

    公开(公告)日：2009-08-18

    申请号：US11044968

    申请日：2005-01-27

    申请人： Hyung-Suk Jung ,  Jong-Ho Lee ,  Hwa-Sung Rhee ,  Jae-Kwang Choi

    发明人： Hyung-Suk Jung ,  Jong-Ho Lee ,  Hwa-Sung Rhee ,  Jae-Kwang Choi

    IPC分类号： H01L23/62

    CPC分类号： H01L21/823857 ,  H01L21/28194 ,  H01L21/3141 ,  H01L21/31608 ,  H01L21/31645 ,  H01L21/823842 ,  H01L29/517 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Integrated circuit devices include a semiconductor substrate having a first doped region and a second doped region having a different doping type than the first doped region. A gate electrode structure on the semiconductor substrate extends between the first and second doped regions and has a gate insulation layer of a first high dielectric constant material in the first doped region and of a second high dielectric constant material, different from the first high dielectric constant material, in the second doped region. A gate electrode is on the gate insulation layer.

    摘要翻译： 集成电路器件包括具有第一掺杂区域和具有与第一掺杂区域不同的掺杂类型的第二掺杂区域的半导体衬底。 半导体衬底上的栅极电极结构在第一和第二掺杂区域之间延伸，并且在第一掺杂区域中具有第一高介电常数材料的栅极绝缘层和不同于第一高介电常数的第二高介电常数材料 材料，在第二掺杂区域。 栅极电极位于栅极绝缘层上。

    Transistors with multilayered dielectric films
    3.
    发明授权
    Transistors with multilayered dielectric films 有权
    具有多层介电膜的晶体管

    公开(公告)号：US08013402B2

    公开(公告)日：2011-09-06

    申请号：US12574912

    申请日：2009-10-07

    申请人： Ha-Jin Lim ,  Jong-Ho Lee ,  Hyung-Suk Jung

    发明人： Ha-Jin Lim ,  Jong-Ho Lee ,  Hyung-Suk Jung

    IPC分类号： H01L21/02

    CPC分类号： H01L21/28185 ,  H01L21/28079 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/823857 ,  H01L29/495 ,  H01L29/513 ,  H01L29/517

    摘要： Transistors that include multilayered dielectric films on a channel region are provided. The multilayered dielectric comprises a lower dielectric film that may have a thickness that is at least 50% the thickness of the multilayered dielectric film and that comprises a metal oxide, a metal silicate, an aluminate, or a mixture thereof, and an upper dielectric film on the lower dielectric film, the upper dielectric film comprising a Group III metal oxide, Group III metal nitride, Group XIII metal oxide or Group XIII metal nitride. A gate electrode is provided on the multilayered dielectric film.

    摘要翻译： 提供了在通道区​​域上包括多层电介质膜的晶体管。 多层电介质包括下电介质膜，该电介质膜的厚度至少为多层电介质膜的厚度的50％，并且包括金属氧化物，金属硅酸盐，铝酸盐或其混合物，以及上电介质膜 在下介电膜上，上电介质膜包含III族金属氧化物，III族金属氮化物，第ⅩⅢ族金属氧化物或第ⅩⅢ族金属氮化物。 在多层电介质膜上设置栅电极。

    Methods of manufacturing a semiconductor device including CMOS transistor having different PMOS and NMOS gate electrode structures
    4.
    发明授权
    Methods of manufacturing a semiconductor device including CMOS transistor having different PMOS and NMOS gate electrode structures 有权
    制造包括具有不同PMOS和NMOS栅电极结构的CMOS晶体管的半导体器件的方法

    公开(公告)号：US07767512B2

    公开(公告)日：2010-08-03

    申请号：US12019449

    申请日：2008-01-24

    申请人： Hyung-Suk Jung ,  Jong-Ho Lee ,  Sung-Kee Han ,  Yun-Ki Choi ,  Ha Jin Lim

    发明人： Hyung-Suk Jung ,  Jong-Ho Lee ,  Sung-Kee Han ,  Yun-Ki Choi ,  Ha Jin Lim

    IPC分类号： H01L21/8238

    CPC分类号： H01L21/823842 ,  H01L21/28026 ,  H01L29/49

    摘要： In a method of manufacturing a semiconductor device, a gate insulation layer is formed on a substrate including a first channel of a first conductive type and a second channel of a second conductive type different from the first conductive type. A first conductive layer including a first metal is formed on the gate insulation layer, and a second conductive layer including a second metal different from the first metal is formed on the first conductive layer formed over the second channel. The second conductive layer is partially removed by a wet etching process to form a second conductive layer pattern over the second channel.

    摘要翻译： 在制造半导体器件的方法中，在包括第一导电类型的第一沟道和不同于第一导电类型的第二导电类型的第二沟道的衬底上形成栅极绝缘层。 在栅极绝缘层上形成包括第一金属的第一导电层，并且在形成在第二沟道上的第一导电层上形成包括不同于第一金属的第二金属的第二导电层。 通过湿式蚀刻工艺部分去除第二导电层，以在第二通道上形成第二导电层图案。

    Dual gate CMOS semiconductor devices and methods of fabricating such devices
    6.
    发明申请
    Dual gate CMOS semiconductor devices and methods of fabricating such devices 审中-公开
    双栅极CMOS半导体器件及其制造方法

    公开(公告)号：US20070034966A1

    公开(公告)日：2007-02-15

    申请号：US11477558

    申请日：2006-06-30

    申请人： Min-Joo Kim ,  Jong-Ho Lee ,  Sung-Kee Han ,  Hyung-Suk Jung

    发明人： Min-Joo Kim ,  Jong-Ho Lee ,  Sung-Kee Han ,  Hyung-Suk Jung

    IPC分类号： H01L29/94

    CPC分类号： H01L21/823842 ,  H01L21/28194 ,  H01L29/4958 ,  H01L29/517 ,  H01L29/518 ,  H01L29/78

    摘要： Disclosed are dual gate CMOS devices and methods for fabricating such devices. The dual gate structures are produced by forming a first gate electrode having first conductive stack on transistors of a first channel type and forming a second gate electrode having a second conductive stack on transistors of a second channel type, wherein the first and second conductive stacks have different compositions for including different work functions (Φ) in the respective transistors. At least one of the first and second conductive stacks will include metal(s) and/or metal compound(s) from which, when subjected to an appropriate thermal treatment, the metal(s) will diffuse to the interface formed between in the gate dielectric layer and the gate electrode and thereby modify the electrical properties of the associated transistors as reflected in, for example, a Vfb shift.

    摘要翻译： 公开了用于制造这种器件的双栅极CMOS器件和方法。 双栅极结构通过在第一沟道型晶体管上形成具有第一导电叠层的第一栅极电极和在第二沟道型晶体管上形成具有第二导电叠层的第二栅极电极而制造，其中第一和第二导电叠层具有 用于在各个晶体管中包括不同功函数（Phi）的不同组合。 第一和第二导电叠层中的至少一个将包括金属和/或金属化合物，当经受适当的热处理时，金属将扩散到在栅极之间形成的界面 电介质层和栅电极，从而改变相关晶体管的电性能，如例如V bias偏移所反映的。

    Transistors with Multilayered Dielectric Films and Methods of Manufacturing Such Transistors
    7.
    发明申请
    Transistors with Multilayered Dielectric Films and Methods of Manufacturing Such Transistors 有权
    具有多层介质膜的晶体管及其制造方法

    公开(公告)号：US20100025781A1

    公开(公告)日：2010-02-04

    申请号：US12574912

    申请日：2009-10-07

    申请人： Ha-Jin Lim ,  Jong-Ho Lee ,  Hyung-Suk Jung

    发明人： Ha-Jin Lim ,  Jong-Ho Lee ,  Hyung-Suk Jung

    IPC分类号： H01L29/78 ,  H01L21/31

    CPC分类号： H01L21/28185 ,  H01L21/28079 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/823857 ,  H01L29/495 ,  H01L29/513 ,  H01L29/517

    摘要： Transistors that include multilayered dielectric films on a channel region are provided. The multilayered dielectric comprises a lower dielectric film that may have a thickness that is at least 50% the thickness of the multilayered dielectric film and that comprises a metal oxide, a metal silicate, an aluminate, or a mixture thereof, and an upper dielectric film on the lower dielectric film, the upper dielectric film comprising a Group III metal oxide, Group III metal nitride, Group XIII metal oxide or Group XIII metal nitride. A gate electrode is provided on the multilayered dielectric film.

    摘要翻译： 提供了在通道区​​域上包括多层电介质膜的晶体管。 多层电介质包括下电介质膜，该电介质膜的厚度至少为多层电介质膜的厚度的50％，并且包括金属氧化物，金属硅酸盐，铝酸盐或其混合物，以及上电介质膜 在下介电膜上，上电介质膜包含III族金属氧化物，III族金属氮化物，第ⅩⅢ族金属氧化物或第ⅩⅢ族金属氮化物。 在多层电介质膜上设置栅电极。

    Transistors with multilayered dielectric films
    8.
    发明授权
    Transistors with multilayered dielectric films 有权
    具有多层介电膜的晶体管

    公开(公告)号：US07615830B2

    公开(公告)日：2009-11-10

    申请号：US11252514

    申请日：2005-10-18

    申请人： Ha-Jin Lim ,  Jong-Ho Lee ,  Hyung-Suk Jung

    发明人： Ha-Jin Lim ,  Jong-Ho Lee ,  Hyung-Suk Jung

    IPC分类号： H01L21/8238

    CPC分类号： H01L21/28185 ,  H01L21/28079 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/823857 ,  H01L29/495 ,  H01L29/513 ,  H01L29/517

    摘要： Transistors that include multilayered dielectric films on a channel region are provided. The multilayered dielectric comprises a lower dielectric film that may have a thickness that is at least 50% the thickness of the multilayered dielectric film and that comprises a metal oxide, a metal silicate, an aluminate, or a mixture thereof, and an upper dielectric film on the lower dielectric film, the upper dielectric film comprising a Group III metal oxide, Group III metal nitride, Group XIII metal oxide or Group XIII metal nitride. A gate electrode is provided on the multilayered dielectric film.

    摘要翻译： 提供了在通道区​​域上包括多层电介质膜的晶体管。 多层电介质包括下电介质膜，该电介质膜的厚度至少为多层电介质膜的厚度的50％，并且包括金属氧化物，金属硅酸盐，铝酸盐或其混合物，以及上电介质膜 在下介电膜上，上电介质膜包含III族金属氧化物，III族金属氮化物，第ⅩⅢ族金属氧化物或第ⅩⅢ族金属氮化物。 在多层电介质膜上设置栅电极。

    Semiconductor devices having nitrogen-incorporated active region and methods of fabricating the same
    9.
    发明授权
    Semiconductor devices having nitrogen-incorporated active region and methods of fabricating the same 有权
    具有氮结合有源区的半导体器件及其制造方法

    公开(公告)号：US07547951B2

    公开(公告)日：2009-06-16

    申请号：US11396702

    申请日：2006-04-04

    申请人： Ha-Jin Lim ,  Jong-Ho Lee ,  Hyung-Suk Jung ,  Yun Seok Kim ,  Min Joo Kim

    发明人： Ha-Jin Lim ,  Jong-Ho Lee ,  Hyung-Suk Jung ,  Yun Seok Kim ,  Min Joo Kim

    IPC分类号： H01L29/78

    CPC分类号： H01L21/823807 ,  H01L21/823857

    摘要： A semiconductor device may include a semiconductor substrate having a first region and a second region. The nitrogen-incorporated active region may be formed within the first region. A first gate electrode may be formed on the nitrogen-incorporated active region. A first gate dielectric layer may be interposed between the nitrogen-incorporated active region and the first gate electrode. The first gate dielectric layer may include a first dielectric layer and a second dielectric layer. The second dielectric layer may be a nitrogen contained dielectric layer. A second gate electrode may be formed on the second region. A second gate dielectric layer may be interposed between the second region and the second gate electrode. The first gate dielectric layer may have the same or substantially the same thickness as the second gate dielectric layer, and the nitrogen contained dielectric layer may contact with the nitrogen-incorporated active region.

    摘要翻译： 半导体器件可以包括具有第一区域和第二区域的半导体衬底。 可以在第一区域内形成含氮的有源区。 可以在引入氮的有源区上形成第一栅电极。 第一栅极电介质层可插入在引入氮的有源区和第一栅电极之间。 第一栅介质层可以包括第一介电层和第二介电层。 第二电介质层可以是含氮介电层。 第二栅极电极可以形成在第二区域上。 可以在第二区域和第二栅电极之间插入第二栅极电介质层。 第一栅极介电层可以具有与第二栅极介电层相同或基本相同的厚度，并且含氮介电层可以与引入氮的有源区接触。

    Transistors with multilayered dielectric films and methods of manufacturing such transistors
    10.
    发明申请
    Transistors with multilayered dielectric films and methods of manufacturing such transistors 有权
    具有多层介电膜的晶体管和制造这种晶体管的方法

    公开(公告)号：US20060081948A1

    公开(公告)日：2006-04-20

    申请号：US11252514

    申请日：2005-10-18

    申请人： Ha-Jin Lim ,  Jong-Ho Lee ,  Hyung-Suk Jung

    发明人： Ha-Jin Lim ,  Jong-Ho Lee ,  Hyung-Suk Jung

    IPC分类号： H01L21/8238 ,  H01L29/94

    CPC分类号： H01L21/28185 ,  H01L21/28079 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/823857 ,  H01L29/495 ,  H01L29/513 ,  H01L29/517

    摘要： Transistors that include multilayered dielectric films on a channel region are provided. The multilayered dielectric comprises a lower dielectric film that may have a thickness that is at least 50% the thickness of the multilayered dielectric film and that comprises a metal oxide, a metal silicate, an aluminate, or a mixture thereof, and an upper dielectric film on the lower dielectric film, the upper dielectric film comprising a Group III metal oxide, Group III metal nitride, Group XIII metal oxide or Group XIII metal nitride. A gate electrode is provided on the multilayered dielectric film.

    摘要翻译： 提供了在通道区​​域上包括多层电介质膜的晶体管。 多层电介质包括下电介质膜，该电介质膜的厚度至少为多层电介质膜的厚度的50％，并且包括金属氧化物，金属硅酸盐，铝酸盐或其混合物，以及上电介质膜 在下介电膜上，上电介质膜包含III族金属氧化物，III族金属氮化物，第ⅩⅢ族金属氧化物或第ⅩⅢ族金属氮化物。 在多层电介质膜上设置栅电极。