公开(公告)号：US20180076103A1

公开(公告)日：2018-03-15

申请号：US15629072

申请日：2017-06-21

Applicant: Hyung-jun JEON ,  Nae-in LEE ,  Byung-lyul PARK

Inventor： Hyung-jun JEON ,  Nae-in LEE ,  Byung-lyul PARK

IPC: H01L23/045 ,  H01L23/047 ,  H01L25/10

CPC classification number: H01L23/045 ,  H01L23/047 ,  H01L23/3128 ,  H01L23/5385 ,  H01L23/5389 ,  H01L24/19 ,  H01L25/105 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2225/1029 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/15311 ,  H01L2924/3511

Abstract: A semiconductor package of a package on package type includes a lower package including a printed circuit board (PCB) substrate including a plurality of base layers and a cavity penetrating the plurality of base layers, a first semiconductor chip in the cavity. a redistribution structure on a first surface of the PCB substrate and on an active surface of the first semiconductor chip, a first cover layer covering the redistribution structure, and the second cover layer covering a second surface of the PCB substrate and an inactive surface of the first semiconductor chip, and an upper package on the second cover layer of the lower package and including a second semiconductor chip.

公开(公告)号：US20160307842A1

公开(公告)日：2016-10-20

申请号：US15006265

申请日：2016-01-26

Applicant: Jong-Min BAEK ,  Sang-Hoon AHN ,  Woo-Kyung YOU ,  Byung-Hee KIM ,  Young-Ju PARK ,  Nae-in LEE ,  Kyung-Min CHUNG

Inventor： Jong-Min BAEK ,  Sang-Hoon AHN ,  Woo-Kyung YOU ,  Byung-Hee KIM ,  Young-Ju PARK ,  Nae-in LEE ,  Kyung-Min CHUNG

IPC: H01L23/522 ,  H01L27/088 ,  H01L23/535 ,  H01L23/532

CPC classification number: H01L27/0886 ,  H01L21/823431 ,  H01L21/823475

Abstract: A semiconductor device includes a plurality of wiring structures spaced apart from each other, and an insulating interlayer structure. Each of the wiring structures includes a metal pattern and a barrier pattern covering a sidewall, a bottom surface, and an edge portion of a top surface of the metal pattern and not covering a central portion of the top surface of the metal pattern. The insulating interlayer structure contains the wiring structures therein, and has an air gap between the wiring structures.

Abstract translation: 半导体器件包括彼此间隔开的多个布线结构和绝缘夹层结构。 每个布线结构包括金属图案和覆盖金属图案的顶表面的侧壁，底表面和边缘部分并且不覆盖金属图案的顶表面的中心部分的阻挡图案。 绝缘层间结构包含其中的布线结构，并且在布线结构之间具有气隙。