公开(公告)号：US09374903B2

公开(公告)日：2016-06-21

申请号：US14210802

申请日：2014-03-14

Applicant: IBIDEN CO., LTD.

Inventor： Naoki Katsuda ,  Naoto Ishida ,  Kota Noda ,  Nobuhisa Kuroda

IPC: H05K1/02 ,  H05K1/18 ,  H05K3/40 ,  H05K3/46

CPC classification number: H05K1/185 ,  H05K3/4007 ,  H05K3/4661 ,  H05K2201/094

Abstract: A multilayer printed wiring board for mounting a semiconductor element includes a core substrate, a first laminated structure on first surface of the substrate and including a conductive circuit layer on the first surface of the substrate, a resin insulating layer and the outermost conductive circuit layer, and a second laminated structure on second surface of the substrate and including a conductive circuit layer on the second surface of the substrate, a resin insulating layer and the outermost conductive circuit layer. The outermost conductive layer in the first structure has solder pads positioned to mount a semiconductor element and solder bumps formed on the pads, respectively, the outermost conductive layer in the second structure has solder pads positioned to mount a wiring board, and the outermost conductive layers in the first and second structures have thicknesses formed greater than thicknesses of the conductive layers on the surfaces of the substrate.

Abstract translation: 用于安装半导体元件的多层印刷线路板包括芯基板，在基板的第一表面上的第一层叠结构，并且在基板的第一表面上包括导电电路层，树脂绝缘层和最外导体电路层， 以及在所述基板的第二表面上的第二层叠结构，并且在所述基板的第二表面上包括导电电路层，树脂绝缘层和最外面的导电电路层。 第一结构中的最外面的导电层具有分别安装半导体元件和形成在焊盘上的焊锡凸块的焊盘，第二结构中的最外面的导电层具有定位成安装布线板的焊盘，并且最外面的导电层 在第一和第二结构中，厚度大于衬底表面上的导电层的厚度。

公开(公告)号：US09661762B2

公开(公告)日：2017-05-23

申请号：US14533329

申请日：2014-11-05

Applicant: IBIDEN CO., LTD.

Inventor： Naoki Katsuda

IPC: H05K1/02 ,  H05K3/46 ,  H05K1/03

CPC classification number: H05K3/4688 ,  H05K1/0271 ,  H05K1/0366 ,  H05K3/4602

Abstract: A printed wiring board includes a core substrate including a resin insulating layer and multiple conductor layers, a first wiring structure formed on a first surface of the core substrate and including a conductor layer and a resin insulating layer, and a second wiring structure formed on a second surface of the core substrate and including a conductor layer and a resin insulating layer. The core substrate is interposed between the first wiring structure and the second wiring structure such that the resin insulating layers and conductor layers in the core substrate, first wiring structure and second wiring structure are alternately laminated, the resin insulating layer in the first wiring structure has a vol % of resin which is larger than a vol % of resin in the resin insulating layer in the second wiring structure such that a difference in the vol % of resin in the first and second wiring structures is in the range of from 0.5% to 5.0%.