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1.发明申请公开(公告)号：US20150008021A1
公开(公告)日：2015-01-08
申请号：US14316966
申请日：2014-06-27
Applicant: IBIDEN CO., LTD.
Inventor： Naoto Ishida , Kota Noda
CPC classification number: H05K3/4015 , H01L2224/16225 , H01L2924/15331 , H05K1/144 , H05K3/4644 , H05K2201/042 , H05K2201/10242
Abstract: A printed wiring board includes an interlayer resin insulation layer, multiple pads formed on the interlayer resin insulation layer, and multiple metal posts having bonding material portions and positioned on the pads, respectively, such that the metal posts are bonded to the pads through the bonding material portions of the metal posts, respectively.
Abstract translation: 印刷电路板包括层间树脂绝缘层，形成在层间树脂绝缘层上的多个焊盘和分别具有接合材料部分并位于焊盘上的多个金属柱，使得金属柱通过键合键合到焊盘 金属柱的材料部分。
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公开(公告)号：US09930791B2
公开(公告)日：2018-03-27
申请号：US14878096
申请日：2015-10-08
Applicant: IBIDEN CO., LTD.
Inventor： Mitsuhiro Tomikawa , Kota Noda , Nobuhisa Kuroda , Haruhiko Morita
IPC: H05K1/16 , H05K3/46 , H01G4/30 , H01G4/12 , H01G4/232 , H05K1/11 , H05K3/42 , H01L23/31 , H01G2/06
CPC classification number: H05K3/4697 , H01G2/06 , H01G4/12 , H01G4/232 , H01G4/30 , H01L23/3128 , H01L2224/16227 , H01L2224/48091 , H01L2224/48227 , H01L2224/73267 , H01L2225/1058 , H01L2924/15331 , H05K1/115 , H05K3/429 , H05K3/4644 , H05K2201/09545 , H05K2201/09827 , H05K2201/10015
Abstract: A wiring board with a built-in electronic component includes a substrate having a cavity, an interlayer insulating layer formed on the substrate such that the interlayer insulating layer is covering the cavity of the substrate, a conductor layer formed on the interlayer insulating layer, an electronic component accommodated in the cavity of the substrate and including a rectangular cuboid body and three terminal electrodes such that each of the three terminal electrodes has a metal film form formed on an outer surface of the rectangular cuboid body, and via conductors formed in the interlayer insulating layer such that the via conductors are connecting the conductor layer and the three terminal electrodes of the electronic component. The three terminal electrodes are arrayed in parallel on the outer surface of the rectangular cuboid body such that adjacent terminal electrodes have the opposite polarities.
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公开(公告)号：US09793200B2
公开(公告)日：2017-10-17
申请号：US14741122
申请日：2015-06-16
Applicant: IBIDEN CO., LTD.
Inventor： Kota Noda , Takeshi Furusawa
CPC classification number: H01L23/49822 , H01L23/49811 , H01L23/49827 , H01L23/49833 , H01L23/49838 , H01L24/13 , H01L24/16 , H01L25/105 , H01L2224/131 , H01L2224/16227 , H01L2224/16237 , H01L2224/81192 , H01L2224/81395 , H01L2224/81411 , H01L2224/81444 , H01L2224/81447 , H01L2224/81464 , H01L2225/1023 , H01L2225/1058 , H01L2225/1088 , H01L2924/15153 , H01L2924/3511 , H01L2924/3512 , H05K1/0271 , H05K3/4697 , H05K2201/09827 , H05K2201/10674 , H01L2924/014 , H01L2924/00014
Abstract: A printed wiring board includes a first circuit board having a first surface and a second surface on the opposite side with respect to the first surface, and a second circuit board having a third surface and a fourth surface on the opposite side with respect to the third surface and having a mounting area on the third surface of the second circuit board. The first circuit board is laminated on the third surface of the second circuit board such that the first surface of the first circuit board faces the third surface of the second circuit board, and the first circuit board includes reinforcing material and has an opening portion exposing the mounting area of the second circuit board.
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公开(公告)号：US09374903B2
公开(公告)日：2016-06-21
申请号：US14210802
申请日：2014-03-14
Applicant: IBIDEN CO., LTD.
Inventor： Naoki Katsuda , Naoto Ishida , Kota Noda , Nobuhisa Kuroda
CPC classification number: H05K1/185 , H05K3/4007 , H05K3/4661 , H05K2201/094
Abstract: A multilayer printed wiring board for mounting a semiconductor element includes a core substrate, a first laminated structure on first surface of the substrate and including a conductive circuit layer on the first surface of the substrate, a resin insulating layer and the outermost conductive circuit layer, and a second laminated structure on second surface of the substrate and including a conductive circuit layer on the second surface of the substrate, a resin insulating layer and the outermost conductive circuit layer. The outermost conductive layer in the first structure has solder pads positioned to mount a semiconductor element and solder bumps formed on the pads, respectively, the outermost conductive layer in the second structure has solder pads positioned to mount a wiring board, and the outermost conductive layers in the first and second structures have thicknesses formed greater than thicknesses of the conductive layers on the surfaces of the substrate.
Abstract translation: 用于安装半导体元件的多层印刷线路板包括芯基板，在基板的第一表面上的第一层叠结构，并且在基板的第一表面上包括导电电路层，树脂绝缘层和最外导体电路层， 以及在所述基板的第二表面上的第二层叠结构，并且在所述基板的第二表面上包括导电电路层，树脂绝缘层和最外面的导电电路层。 第一结构中的最外面的导电层具有分别安装半导体元件和形成在焊盘上的焊锡凸块的焊盘，第二结构中的最外面的导电层具有定位成安装布线板的焊盘，并且最外面的导电层 在第一和第二结构中，厚度大于衬底表面上的导电层的厚度。
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公开(公告)号：US09917025B2
公开(公告)日：2018-03-13
申请号：US14741011
申请日：2015-06-16
Applicant: IBIDEN CO., LTD.
Inventor： Kota Noda , Takeshi Furusawa
CPC classification number: H01L23/13 , H01L23/49811 , H01L23/49822 , H01L23/49827 , H01L23/49833 , H01L23/49838 , H01L24/13 , H01L24/16 , H01L25/105 , H01L2224/131 , H01L2224/16227 , H01L2224/16237 , H01L2224/81192 , H01L2224/81395 , H01L2224/81411 , H01L2224/81444 , H01L2224/81447 , H01L2224/81464 , H01L2225/1023 , H01L2225/1058 , H01L2225/1088 , H01L2924/15153 , H01L2924/3511 , H01L2924/3512 , H05K1/0271 , H05K3/4697 , H05K2201/09827 , H05K2201/10674 , Y10T29/49158 , H01L2924/014 , H01L2924/00014
Abstract: A printed wiring board includes a first circuit board having a first surface and a second surface, and a second circuit board having a third surface and a fourth surface and having a mounting area on the third surface of the second circuit board. The first circuit board is laminated on the third surface of the second circuit board such that the first surface of the first circuit board is in contact with the third surface of the second circuit board, the first circuit board includes reinforcing material and has an opening portion exposing the mounting area of the second circuit board, and the first circuit board and the second circuit board are formed such that a ratio H1/h1 is in a range that is greater than 0.75 and smaller than 2.4, where H1 represents a thickness of the first circuit board and h1 represents a thickness of the second circuit board.
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Patent Agency Ranking
公开(公告)号：US09837345B2
公开(公告)日：2017-12-05
申请号：US15211332
申请日：2016-07-15
Applicant: IBIDEN CO., LTD.
Inventor： Kota Noda , Takema Adachi
IPC: H01L23/498 , H01L21/48 , H01L25/065 , H01L23/00 , H01L25/10
CPC classification number: H01L23/49838 , H01L21/4857 , H01L23/49822 , H01L23/49827 , H01L23/49833 , H01L23/49894 , H01L23/562 , H01L24/16 , H01L24/48 , H01L24/73 , H01L25/0655 , H01L25/105 , H01L2224/16227 , H01L2224/16235 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2225/1023 , H01L2225/1058 , H01L2225/107 , H01L2924/00014 , H01L2924/14 , H01L2924/1434 , H01L2924/15311 , H01L2924/15331 , H01L2924/3511 , H01L2924/3512 , H01L2224/32225 , H01L2924/00012 , H01L2224/45099
Abstract: An interposer includes an insulating plate including insulating layers and having first, second, third and fourth surfaces such that the second surface is on the opposite side of the first surface, the third surface is perpendicular to the first surface, the fourth surface is on the opposite side of the third surface, and the insulating layers are laminated on the third surface, and conductor layers formed in the insulating plate such that each conductor layer is interposed between adjacent insulating layers and includes straight conductors having first electrodes exposed from the first surface and second electrodes exposed from the second surface, respectively. The insulating layers include second insulating layers each sandwiched by adjacent conductor layers such that each second insulating layer integrally has an inter-conductor-layer insulating layer portion formed between the adjacent conductor layers and inter-conductor insulating layer portions formed between adjacent straight conductors in a respective conductor layer.
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公开(公告)号：US09704795B2
公开(公告)日：2017-07-11
申请号：US14820963
申请日：2015-08-07
Applicant: IBIDEN CO., LTD.
Inventor： Yasushi Inagaki , Kota Noda
CPC classification number: H01L23/49838 , H01L21/4857 , H01L23/49811 , H01L23/49827 , H01L2924/0002 , H05K1/0278 , H05K1/111 , H05K3/4015 , H05K2201/0376 , H05K2201/09827 , H01L2924/00
Abstract: A printed wiring board includes an insulating layer, a first conductor layer embedded into first surface of the insulating layer and including multiple wirings such that the wirings include connecting portions positioned to connect an electronic component, respectively, a second conductor layer projecting from second surface of the insulating layer on the opposite side, a solder resist layer formed on the first surface of the insulating layer such that the solder resist layer is covering the first conductor layer and has an opening structure exposing the connecting portions of the wirings, and multiple metal posts formed on the connecting portions respectively such that each of the metal posts has a width which is larger than a width of a respective one of the wirings having the connecting portions. The wirings are formed such that the connecting portions are positioned side by side on every other adjacent one of the wirings.
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公开(公告)号：US10221497B2
公开(公告)日：2019-03-05
申请号：US14663559
申请日：2015-03-20
Applicant: IBIDEN CO., LTD.
Inventor： Kota Noda , Takema Adachi , Wataru Nakamura
IPC: C25D5/02 , C25D7/12 , C25D7/00 , C23C18/16 , H05K3/40 , C25D5/10 , C25D5/12 , C23C18/38 , H05K3/10 , H05K3/24 , H05K3/46
Abstract: A method for manufacturing a wiring board having conductive posts includes preparing a wiring board including electronic circuit and a solder resist layer covering the electronic circuit and having first openings and second openings surrounding the first openings such that the first openings are exposing pad portions of the electronic circuit and that the second openings are exposing post connecting portions of the electronic circuit surrounding the pad portions, applying surface treatment to the pad portions, forming a plating resist layer on the wiring board after the surface treatment of the pad portions such that the plating resist layer has resist openings exposing the post connecting portions, applying electrolytic plating on the post connecting portions such that conductive posts rising from the post connecting portions are formed in the resist openings, and removing the plating resist layer from the wiring board after forming the conductive posts in the resist openings.
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公开(公告)号：US09743534B2
公开(公告)日：2017-08-22
申请号：US14878072
申请日：2015-10-08
Applicant: IBIDEN CO., LTD.
Inventor： Mitsuhiro Tomikawa , Kota Noda , Nobuhisa Kuroda , Haruhiko Morita
CPC classification number: H05K3/4697 , H01L2224/16227 , H01L2224/16265 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2225/1023 , H01L2225/1058 , H01L2924/15311 , H01L2924/15331 , H01L2924/181 , H05K1/141 , H05K1/185 , H05K3/0038 , H05K3/427 , H05K3/4602 , H05K3/4644 , H05K2201/10015 , H05K2203/1476 , H01L2924/00014 , H01L2224/32225 , H01L2924/00012
Abstract: A wiring board with a built-in electronic component includes a substrate having cavity, an insulating layer formed on the substrate such that the insulating layer is covering the cavity, a conductor layer formed on the insulating layer, and an electronic component accommodated in the cavity and including a rectangular cuboid body and terminal electrodes such that each electrode has a metal film form formed on outer surface of the body, and via conductors formed in the insulating layer such that the via conductors are connecting the conductor layer and electrodes. The electrodes are arrayed in a matrix having rows and columns such that adjacent electrodes in row and column directions have the opposite polarities, and the conductor layer includes a line pattern shunting first group of the electrodes in one polarity and a solid pattern shunting second group of the electrodes in the other polarity.
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公开(公告)号：US09723729B2
公开(公告)日：2017-08-01
申请号：US14920974
申请日：2015-10-23
Applicant: IBIDEN CO., LTD.
Inventor： Takeshi Furusawa , Kota Noda
IPC: H05K1/11 , H05K1/02 , H05K1/09 , H05K3/46 , H01L23/13 , H05K1/18 , H05K3/00 , H01L23/498 , H01L21/48
CPC classification number: H05K3/4697 , H01L21/4857 , H01L21/486 , H01L23/13 , H01L23/49822 , H01L23/49827 , H01L23/49838 , H01L2224/16227 , H01L2224/16235 , H01L2225/1023 , H01L2225/1058 , H01L2924/15311 , H05K1/0298 , H05K1/09 , H05K1/115 , H05K1/18 , H05K1/183 , H05K3/0097 , H05K3/4602 , H05K2201/10674 , H05K2203/107
Abstract: A printed wiring board includes a substrate, a first conductor layer formed on first surface of the substrate, a second conductor layer formed on second surface of the substrate, a through-hole conductor penetrating through the substrate and connecting the first and second conductor layers, a build-up layer formed on the second surface of the substrate and including conductor layers, insulating layers and via conductors, and a first insulating layer formed on the first surface the substrate and covering the first conductor layer. The substrate has a cavity penetrating through the first insulating layer and substrate and exposing the build-up layer on the substrate, the via conductors include a lowermost via conductor having a bottom portion exposed at bottom of the cavity, and the bottom portion of the lowermost via conductor is recessed relative to surface of a lowermost insulating layer in the build-up layer at the bottom of the cavity.
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