公开(公告)号：US3582878A

公开(公告)日：1971-06-01

申请号：US3582878D

申请日：1969-01-08

Applicant: IBM ,  ROBERT T CHIEN

Inventor： BOSSEN DOUGLAS C ,  CHIEN ROBERT T ,  HSIAO MU-YUE ,  SELLERS FREDERICK F JR

IPC: H03M13/19 ,  H04L1/00 ,  H04L1/10 ,  G08C25/00

CPC classification number: H04L1/0057 ,  H03M13/19 ,  H04L1/0041

Abstract: The error correcting system is capable of correcting multiple random errors in data messages of k m2 data bits where m is an integer. The message is encoded by adding 2m check bits for each additional error correcting capability. The encoded message after data transfer and storage is decoded by parity checking and threshold logic decision circuits. The parity checking circuits are constructed in modular form. Each additional module adds a further error correcting capability. The outputs from each module form inputs to the threshold logic decision circuit where the error correction is made. Detection of an additional error can be simply achieved by an overall parity circuit.

公开(公告)号：US3508196A

公开(公告)日：1970-04-21

申请号：US3508196D

申请日：1968-12-06

Applicant: IBM

Inventor： SELLERS FREDERICK F JR ,  BROWN DAVID T

IPC: H03M13/15 ,  G08B29/00 ,  G06F11/00

CPC classification number: H03M13/15

公开(公告)号：US3508195A

公开(公告)日：1970-04-21

申请号：US3508195D

申请日：1964-04-06

Applicant: IBM

Inventor： SELLERS FREDERICK F JR

IPC: G11B27/28 ,  G06F13/24 ,  G06F15/78 ,  G11B20/12 ,  G11B20/18 ,  G08B29/00 ,  G06F11/00 ,  G08B1/00

CPC classification number: G11B20/1833 ,  G06F13/24 ,  G06F15/78