Abstract:
A data storage unit is provided in which groups or ''''pages'''' of data including their addresses are stored in shift registers in successive positions, the registers being operable on a signal requesting access to shift their contents repetitively to the next position in one or more loops which include a position wherein a page may be accessed and in one or more loops which excludes said access position. Controls are provided for varying the shifting in said loops such that the positions of some or all of the pages of separately accessed classes are dynamically reordered so that they are presented to said access position on such signal in approximately or exactly the order in which they were last requested, thus reducing average access time in programs involving considerable repeated reference to a limited group of pages of the class.
Abstract:
This specification discloses a bubble domain memory in which data is arranged for immediacy of access in accordance with its last use. The memory comprises a plurality of parallel shift registers in which data can be accessed in parallel. In other words, each of the shift registers contains a bit of a page or word so that by the performance of one shifting operation all of the bits of the page or word can be accessed. Data in each shift register is arranged in its order of last use so that the access position K of a shift register having K bit positions contains the last bit of information used and the position K-1 preceding the access position K in the shift register contains the bit of data used just previously to the data in the access position K and so on. In these shift registers the shift positions are arranged in loops for shifting the data between the positions of the shift register. Two such loops are provided, one of the loops contains all the shift positions so that data in any position in the shift register can be shifted into the access position K of the register for reading or writing. The other loop contains all the positions of the shift register but the access position K. This second loop is for reordering the data in the shift register in order of last use after data has been shifted into the access position K for reading or writing by the first loop.