公开(公告)号：US09374047B2

公开(公告)日：2016-06-21

申请号：US14455991

申请日：2014-08-11

Applicant: ILI TECHNOLOGY CORP.

Inventor： Chih-Kang Cheng ,  Tzung-Yun Tsai

IPC: H03F3/45 ,  H03F1/02 ,  H03F3/21 ,  H03F1/30 ,  H03F3/30

CPC classification number: H03F3/45179 ,  H03F1/0277 ,  H03F1/307 ,  H03F3/211 ,  H03F3/30 ,  H03F3/3022 ,  H03F3/45 ,  H03F3/45475 ,  H03F2203/45138

Abstract: The present disclosure provides a buffer circuit comprising a plurality of operational amplifiers and a switch module. Each operational amplifier forms a buffer. The operational amplifier has an output stage. The stage has a first transistor and a second transistor. The first transistor and the second transistor are connected to an output terminal. The first transistor has a first control terminal. The second transistor has a second control terminal. The switch module is connected to the first control terminal of the first transistor and the second control terminal of the second transistor. The switch module connects together at least two of the first terminals of the first transistor according to a control signal. The switch module connects together at least two of the second terminals of the second transistor according to the control signal.

Abstract translation: 本公开提供了一种包括多个运算放大器和开关模块的缓冲电路。 每个运算放大器形成缓冲器。 运算放大器有一个输出级。 该级具有第一晶体管和第二晶体管。 第一晶体管和第二晶体管连接到输出端。 第一晶体管具有第一控制端。 第二晶体管具有第二控制端子。 开关模块连接到第一晶体管的第一控制端和第二晶体管的第二控制端。 开关模块根据控制信号将第一晶体管的至少两个第一端子连接在一起。 开关模块根据控制信号将第二晶体管的至少两个第二端子连接在一起。