公开(公告)号：US10510774B2

公开(公告)日：2019-12-17

申请号：US15479633

申请日：2017-04-05

Applicant: IMEC VZW

Inventor： Peter Debacker ,  Praveen Raghavan ,  Vassilios Constantinos Gerousis

IPC: H01L27/118 ,  H01L23/528 ,  H01L27/02

Abstract: An integrated circuit (IC) power distribution network is disclosed. In one aspect, the IC includes a stack of layers formed on a substrate. The IC includes standard cells with parallel gate structures oriented in a direction y. Each cell includes an internal power pin for supplying a reference voltage to the cell. The stack includes metal layers in which lines are formed to route signals between cells. The lines in each metal layer have a preferred orientation that is orthogonal to that of the lines in an adjacent metal layer. A first layer is the lowest metal layer that has y as a preferred orientation while also providing routing resources for signal routing between the cells. A second layer is the nearest metal layer above this first layer. The IC includes a power distribution network for delivering the reference voltage to the power pin.

公开(公告)号：US20220076737A1

公开(公告)日：2022-03-10

申请号：US17447131

申请日：2021-09-08

Applicant: IMEC vzw

Inventor： Stefan Cosemans ,  Ioannis Papistas ,  Peter Debacker

IPC: G11C11/4096 ,  G11C11/4094 ,  G11C11/4074 ,  H03K7/08 ,  G06F17/16 ,  G06N20/00

Abstract: A compute cell for in-memory multiplication of a digital data input and a balanced ternary weight, and an in-memory computing device including an array of the compute cells, are provided. In one aspect, the compute cell includes a set of input connectors for receiving modulated input signals representative of a sign and a magnitude of the data input, and a memory unit configured to store the ternary weight. A logic unit connected to the set of input connectors and the memory unit receives the data input and the ternary weight. The logic unit selectively enables one of a plurality of conductive paths for supplying a partial charge to a read bit line during a compound duty cycle of the set of input signals as a function of the respective signs of data input and ternary weight, and disables each of the plurality of conductive paths if at least one of the ternary weight and data input have zero magnitude.

公开(公告)号：US11699482B2

公开(公告)日：2023-07-11

申请号：US17447131

申请日：2021-09-08

Applicant: IMEC vzw

Inventor： Stefan Cosemans ,  Ioannis Papistas ,  Peter Debacker

IPC: G11C11/54 ,  G11C11/4096 ,  G06N20/00 ,  G06F17/16 ,  G11C11/4074 ,  G11C11/4094 ,  H03K7/08 ,  G06J1/00 ,  G11C11/419 ,  G11C11/413 ,  G11C27/00

CPC classification number: G11C11/4096 ,  G06F17/16 ,  G06J1/00 ,  G06N20/00 ,  G11C11/4074 ,  G11C11/4094 ,  G11C11/413 ,  G11C11/419 ,  G11C11/54 ,  G11C27/00 ,  H03K7/08

Abstract: A compute cell for in-memory multiplication of a digital data input and a balanced ternary weight, and an in-memory computing device including an array of the compute cells, are provided. In one aspect, the compute cell includes a set of input connectors for receiving modulated input signals representative of a sign and a magnitude of the data input, and a memory unit configured to store the ternary weight. A logic unit connected to the set of input connectors and the memory unit receives the data input and the ternary weight. The logic unit selectively enables one of a plurality of conductive paths for supplying a partial charge to a read bit line during a compound duty cycle of the set of input signals as a function of the respective signs of data input and ternary weight, and disables each of the plurality of conductive paths if at least one of the ternary weight and data input have zero magnitude.

公开(公告)号：US20180144240A1

公开(公告)日：2018-05-24

申请号：US15820239

申请日：2017-11-21

Applicant: IMEC VZW ,  Katholieke Universiteit Leuven

Inventor： Daniele Garbin ,  Dimitrios Rodopoulos ,  Peter Debacker ,  Praveen Raghavan

IPC: G06N3/063 ,  G06N3/04

CPC classification number: G06N3/063 ,  G06N3/04 ,  G06N3/0454 ,  G11C11/1659 ,  G11C11/54 ,  G11C13/003 ,  G11C2213/79 ,  H03K19/168

Abstract: The disclosed technology generally relates to machine learning, and more particularly to integration of basic machine learning kernels in a semiconductor device. In an aspect, a semiconductor cell is configured to perform one or more logic operations such as one or both of an XNOR and an XOR operation. The semiconductor cell includes a memory unit configured to store a first operand, an input port unit configured to receive a second operand and a switch unit configured to implement one or more logic operations on the stored first operand and the received second operand. The semiconductor cell additionally includes a readout port configured to provide an output of one or more logic operations. A plurality of cells may be organized in an array, and one or more of such arrays may be used to implement a neural network.

公开(公告)号：US20170294448A1

公开(公告)日：2017-10-12

申请号：US15479633

申请日：2017-04-05

Applicant: IMEC VZW

Inventor： Peter Debacker ,  Praveen Raghavan ,  Vassilios Constantinos Gerousis

IPC: H01L27/118

Abstract: An integrated circuit (IC) power distribution network is disclosed. In one aspect, the IC includes a stack of layers formed on a substrate. The IC includes standard cells with parallel gate structures oriented in a direction y. Each cell includes an internal power pin for supplying a reference voltage to the cell. The stack includes metal layers in which lines are formed to route signals between cells. The lines in each metal layer have a preferred orientation that is orthogonal to that of the lines in an adjacent metal layer. A first layer is the lowest metal layer that has y as a preferred orientation while also providing routing resources for signal routing between the cells. A second layer is the nearest metal layer above this first layer. The IC includes a power distribution network for delivering the reference voltage to the power pin.