公开(公告)号：US12163989B2

公开(公告)日：2024-12-10

申请号：US17559371

申请日：2021-12-22

Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE

Inventor： Sih-Han Li ,  Jie Zhang ,  Peng-I Mei

IPC: G01R27/32 ,  G01R35/00

Abstract: A high-frequency component test device including a test key and a test module is provided. The test key includes a front-level key and a back-level key which are arranged symmetrically and have the same electrical length and characteristic impedance. The test module is used to measure an S parameter of the front-level key and the back-level key connected directly and an S parameter of a structure where a device under test (DUT) is added between the front-level key and the back-level key. The test module performs S parameter calculation in the frequency domain and converts the S parameter into an ABCD parameter matrix, and then obtains an ABCD parameter of a de-embedded DUT using a matrix root-opening operation and an inverse matrix operation.

公开(公告)号：US20220413801A1

公开(公告)日：2022-12-29

申请号：US17679090

申请日：2022-02-24

Applicant: Industrial Technology Research Institute

Inventor： Jian-Wei Su ,  Chih-Sheng Lin ,  Peng-I Mei ,  Sih-Han Li ,  Shyh-Shyuan Sheu ,  Jheng Yang Dai

IPC: G06F7/523 ,  G06F7/50

Abstract: A configurable computing unit within memory including a first input transistor, a first weight transistor, a first resistor, a second input transistor, a second weight transistor, and a second resistor is provided. The first input transistor, the first weight transistor, and the first resistor are coupled in series between a first readout bit line and a common signal line. The first input transistor is coupled to a first input bit line, and the first weight transistor receives a first weight bit. The second input transistor, the second weight transistor, and the second resistor are coupled in series between the first readout bit line and the common signal line. The second input transistor is coupled to a second input bit line, and the second weight transistor receives the second weight bit.