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公开(公告)号：US20180136010A1
公开(公告)日：2018-05-17
申请号：US15607389
申请日：2017-05-26
Applicant: Industrial Technology Research Institute
Inventor： Sih-Han Li , Shyh-Shyuan Sheu , Ya-Wen Yang , Chih-Ping Cheng , Chih-Sheng Lin
CPC classification number: G01D3/022 , G01B2210/60 , G01D18/008 , H03K17/30
Abstract: A sensor interface circuit and sensor output adjusting method are provided. The sensor interface circuit includes a processor and a gain control circuit. The processor obtains information of a linear region of a sensor to set a configuration corresponding to the sensor. The gain control circuit is coupled to the processor, performs a return-to-zero operation for a maximum electronic value and a minimum electronic value corresponding to the linear region and performs a full-scale operation for a slope of the linear region according to the maximum input range of an analog-to-digital converter which is a subsequent-stage circuit of the sensor interface circuit.
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公开(公告)号：US09368271B2
公开(公告)日：2016-06-14
申请号：US14693866
申请日：2015-04-22
Applicant: Industrial Technology Research Institute
Inventor： Sih-Han Li , Chih-Sheng Lin
CPC classification number: H01F27/2804 , H01F5/00 , H01F27/2823 , H01F27/29 , H01F2027/2809
Abstract: First and second paths of the primary-coil of the transformer are located at different sides of the symmetry-line. First terminals of the first and second paths are first and second ports of the primary-coil. Second terminals of the first and second paths are connected to each other. Two partial paths of the first path are connected to each other by TSV. Two partial paths of the second path are connected to each other by TSV. Third and fourth paths of the secondary-coil of the transformer are located on different sides of the symmetry-line. First terminals of the third and fourth paths are first and second ports of the secondary-coil. Second terminals of the third and fourth paths are connected to each other. Two partial paths of the third path are connected to each other by TSV. Two partial paths of the fourth path are connected to each other by TSV.
Abstract translation: 变压器的初级线圈的第一和第二路径位于对称线的不同侧。 第一和第二路径的第一端子是初级线圈的第一和第二端口。 第一和第二路径的第二端子彼此连接。 第一路径的两个部分路径通过TSV相互连接。 第二路径的两个部分路径通过TSV相互连接。 变压器的次级线圈的第三和第四路径位于对称线的不同侧。 第三和第四路径的第一端子是次级线圈的第一和第二端口。 第三和第四路径的第二端子彼此连接。 第三路径的两个部分路径通过TSV相互连接。 第四路径的两个部分路径通过TSV相互连接。
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公开(公告)号：US20160012958A1
公开(公告)日：2016-01-14
申请号：US14693866
申请日：2015-04-22
Applicant: Industrial Technology Research Institute
Inventor： Sih-Han Li , Chih-Sheng Lin
CPC classification number: H01F27/2804 , H01F5/00 , H01F27/2823 , H01F27/29 , H01F2027/2809
Abstract: First and second paths of the primary-coil of the transformer are located at different sides of the symmetry-line. First terminals of the first and second paths are first and second ports of the primary-coil. Second terminals of the first and second paths are connected to each other. Two partial paths of the first path are connected to each other by TSV. Two partial paths of the second path are connected to each other by TSV. Third and fourth paths of the secondary-coil of the transformer are located on different sides of the symmetry-line. First terminals of the third and fourth paths are first and second ports of the secondary-coil. Second terminals of the third and fourth paths are connected to each other. Two partial paths of the third path are connected to each other by TSV. Two partial paths of the fourth path are connected to each other by TSV.
Abstract translation: 变压器的初级线圈的第一和第二路径位于对称线的不同侧。 第一和第二路径的第一端子是初级线圈的第一和第二端口。 第一和第二路径的第二端子彼此连接。 第一路径的两个部分路径通过TSV相互连接。 第二路径的两个部分路径通过TSV相互连接。 变压器的次级线圈的第三和第四路径位于对称线的不同侧。 第三和第四路径的第一端子是次级线圈的第一和第二端口。 第三和第四路径的第二端子彼此连接。 第三路径的两个部分路径通过TSV相互连接。 第四路径的两个部分路径通过TSV相互连接。
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公开(公告)号：US12231086B2
公开(公告)日：2025-02-18
申请号：US18097933
申请日：2023-01-17
Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
Inventor： Jie Zhang , Sih-Han Li
IPC: H03D7/14
Abstract: A switching circuit includes a transmission gate, two base control sub-circuits each including a first transistor and a second transistor, a third transistor, and a fourth transistor. The transmission gate includes two I/O terminals, two gate control terminals, and two base control terminals, and is configured to conduct or not conduct the two I/O terminals according to the voltage of the two gate control terminals. The two base voltage control sub-circuits, the third transistor and the fourth transistor forms a double balance circuit structure and is electrically connected to the transmission gate. The double balance circuit changes the voltage of the base control terminals according to the voltage of the I/O terminals of the transmission gate.
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公开(公告)号：US12163989B2
公开(公告)日：2024-12-10
申请号：US17559371
申请日：2021-12-22
Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
Inventor： Sih-Han Li , Jie Zhang , Peng-I Mei
Abstract: A high-frequency component test device including a test key and a test module is provided. The test key includes a front-level key and a back-level key which are arranged symmetrically and have the same electrical length and characteristic impedance. The test module is used to measure an S parameter of the front-level key and the back-level key connected directly and an S parameter of a structure where a device under test (DUT) is added between the front-level key and the back-level key. The test module performs S parameter calculation in the frequency domain and converts the S parameter into an ABCD parameter matrix, and then obtains an ABCD parameter of a de-embedded DUT using a matrix root-opening operation and an inverse matrix operation.
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Patent Agency Ranking
公开(公告)号：US12154905B2
公开(公告)日：2024-11-26
申请号：US17372132
申请日：2021-07-09
Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
Inventor： Jie Zhang , Tai-Hsing Lee , Sih-Han Li
IPC: H01L27/118 , H01L25/065 , H03K17/60 , H03K17/687 , H01L23/00
Abstract: An arrayed switch circuit includes a substrate, signal conductive pads and signal expansion pins. The signal conductive pads are disposed on the substrate at intervals, and the signal conductive pads are arranged to form a signal conductive pad array. Each of the signal conductive pads has a row position and a column position in the signal conductive pad array. A row signal switch is provided between any two adjacent signal conductive pads corresponding to the same row position, and a column signal switch is provided between any two adjacent signal conductive pads corresponding to the same column position. The signal expansion pins are connected to the signal conductive pads located on at least one side of the signal conductive pad array through signal expansion switches respectively.
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公开(公告)号：US10914618B2
公开(公告)日：2021-02-09
申请号：US15851609
申请日：2017-12-21
Applicant: Industrial Technology Research Institute
Inventor： Sih-Han Li , Chih-Sheng Lin , Ya-Wen Yang , Kuan-Wei Chen , Shyh-Shyuan Sheu
Abstract: A readout circuit for a sensor and a readout method thereof are provided. The readout circuit includes a reference circuit, a compensated circuit, and a signal processing circuit. The reference circuit provides a direct current (DC) signal. The compensated circuit is coupled to the reference circuit. The compensated circuit obtains an analog sensing signal of the sensor, obtains the DC signal from the reference circuit, and provides a compensated signal according to the analog sensing signal and the DC signal. The signal processing circuit is coupled to the compensated circuit. The signal processing circuit processes the compensated signal to convert the compensated signal into a digital sensing signal. The compensated circuit subtracts the DC signal from the analog sensing signal to provide the compensated signal.
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公开(公告)号：US20210004678A1
公开(公告)日：2021-01-07
申请号：US16846427
申请日：2020-04-13
Applicant: Industrial Technology Research Institute
Inventor： Shih-Chieh Chang , Sih-Han Li , Shyh-Shyuan Sheu , Jian-Wei Su , Heng-Yuan Lee
Abstract: A neural circuit is provided. The neural circuit includes a neural array. The neural array includes a plurality of semiconductor components. Each of the semiconductor components stores a weighting value to generate a corresponding output current or a corresponding equivalent resistance. The neural array receives a plurality of input signals to control the semiconductor components in the neural array and respectively generates the output currents or changes the equivalent resistances. Since the semiconductor components are coupled to each other, output of the neural array may generate a summation current or a summation equivalent resistance related to the input signals and a weighting condition, so that a computing result exhibits high performance.
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公开(公告)号：US11741189B2
公开(公告)日：2023-08-29
申请号：US18155762
申请日：2023-01-18
Applicant: Industrial Technology Research Institute
Inventor： Chih-Sheng Lin , Jian-Wei Su , Tuo-Hung Hou , Sih-Han Li , Fu-Cheng Tsai , Yu-Hui Lin
IPC: G11C11/412 , G06F17/16
CPC classification number: G06F17/16 , G11C11/412
Abstract: A computing in memory (CIM) cell includes a memory cell circuit, a first semiconductor element, a second semiconductor element, a third semiconductor element, and a fourth semiconductor element. A first terminal of the first semiconductor element receives a bias voltage. A control terminal of the first semiconductor element is coupled to a computing word-line. A control terminal of the second semiconductor element is coupled to a first data node in the memory cell circuit. A second terminal of the third semiconductor element is adapted to receive a reference voltage. A control terminal of the third semiconductor element receives an inverted signal of the computing word-line. A first terminal of the fourth semiconductor element is coupled to a first computing bit-line. A second terminal of the fourth semiconductor element is coupled to a second computing bit-line.
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公开(公告)号：US20210397675A1
公开(公告)日：2021-12-23
申请号：US17013646
申请日：2020-09-06
Applicant: Industrial Technology Research Institute
Inventor： Chih-Sheng Lin , Jian-Wei Su , Tuo-Hung Hou , Sih-Han Li , Fu-Cheng Tsai , Yu-Hui Lin
IPC: G06F17/16 , G11C11/412
Abstract: A computing in memory (CIM) cell includes a memory cell circuit, a first semiconductor element, a second semiconductor element, and a third semiconductor element. A first terminal of the first semiconductor element is coupled to a first computing bit-line. A control terminal of the first semiconductor element is coupled to a computing word-line. A control terminal of the second semiconductor element is coupled to the memory cell circuit. A first terminal of the second semiconductor element is coupled to a second terminal of the first semiconductor element. A first terminal of the third semiconductor element is coupled to a second terminal of the second semiconductor element. A second terminal of the third semiconductor element is coupled to a second computing bit-line. A control terminal of the third semiconductor element receives a bias voltage.
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