公开(公告)号：US20180181529A1

公开(公告)日：2018-06-28

申请号：US15390344

申请日：2016-12-23

Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE

Inventor： Chao-Tang LEE ,  Peng-Kai HSU

IPC: G06F13/42 ,  G06F13/38 ,  G06F13/36

CPC classification number: G06F13/4221 ,  G06F13/36 ,  G06F13/385 ,  G06F13/404 ,  G06F13/4234 ,  G06F2213/0024 ,  G06F2213/0026

Abstract: A ring network system using peripheral component interconnect express (PCIe) is disclosed. The ring network system includes N PCIe bridges. Each of the N PCIe bridges is connected to an individual server and includes a first port and a second port. The second port of an ith PCIe bridge of the N PCIe bridges is connected to the first port of an ((i+1) mod N)th PCIe bridge of the N PCIe bridges. Each of the N PCIe bridges includes an address mapping chip. The address mapping chip of each of the N PCIe bridges configurably maps to a system address of each of at least portion of N servers connected by the N PCIe bridges and configurably maps to an address of each of at least portion of the N PCIe bridges for setting up a mapping relationship between the N PCIe bridges.

公开(公告)号：US20180341607A1

公开(公告)日：2018-11-29

申请号：US16053605

申请日：2018-08-02

Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE

Inventor： Chao-Tang LEE ,  Peng-Kai HSU

IPC: G06F13/40 ,  G06F13/42

CPC classification number: G06F13/404 ,  G06F13/4282 ,  G06F2213/0026

Abstract: A ring network system using peripheral component interconnect express (PCIe) is disclosed. The ring network system includes N PCIe bridges. Each of the N PCIe bridges is connected to an individual server and includes a first port and a second port. The second port of an ith PCIe bridge of the N PCIe bridges is connected to the first port of an ((i mod N)+1)th PCIe bridge of the N PCIe bridges. Each of the N PCIe bridges includes an address mapping chip. The address mapping chip of each of the N PCIe bridges configurably maps to a system address of each of at least portion of N servers connected by the N PCIe bridges and configurably maps to an address of each of at least portion of the N PCIe bridges for setting up a mapping relationship between the N PCIe bridges.