公开(公告)号：US20180341607A1

公开(公告)日：2018-11-29

申请号：US16053605

申请日：2018-08-02

Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE

Inventor： Chao-Tang LEE ,  Peng-Kai HSU

IPC: G06F13/40 ,  G06F13/42

CPC classification number: G06F13/404 ,  G06F13/4282 ,  G06F2213/0026

Abstract: A ring network system using peripheral component interconnect express (PCIe) is disclosed. The ring network system includes N PCIe bridges. Each of the N PCIe bridges is connected to an individual server and includes a first port and a second port. The second port of an ith PCIe bridge of the N PCIe bridges is connected to the first port of an ((i mod N)+1)th PCIe bridge of the N PCIe bridges. Each of the N PCIe bridges includes an address mapping chip. The address mapping chip of each of the N PCIe bridges configurably maps to a system address of each of at least portion of N servers connected by the N PCIe bridges and configurably maps to an address of each of at least portion of the N PCIe bridges for setting up a mapping relationship between the N PCIe bridges.

公开(公告)号：US20180181529A1

公开(公告)日：2018-06-28

申请号：US15390344

申请日：2016-12-23

Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE

Inventor： Chao-Tang LEE ,  Peng-Kai HSU

IPC: G06F13/42 ,  G06F13/38 ,  G06F13/36

CPC classification number: G06F13/4221 ,  G06F13/36 ,  G06F13/385 ,  G06F13/404 ,  G06F13/4234 ,  G06F2213/0024 ,  G06F2213/0026

Abstract: A ring network system using peripheral component interconnect express (PCIe) is disclosed. The ring network system includes N PCIe bridges. Each of the N PCIe bridges is connected to an individual server and includes a first port and a second port. The second port of an ith PCIe bridge of the N PCIe bridges is connected to the first port of an ((i+1) mod N)th PCIe bridge of the N PCIe bridges. Each of the N PCIe bridges includes an address mapping chip. The address mapping chip of each of the N PCIe bridges configurably maps to a system address of each of at least portion of N servers connected by the N PCIe bridges and configurably maps to an address of each of at least portion of the N PCIe bridges for setting up a mapping relationship between the N PCIe bridges.

公开(公告)号：US20160077848A1

公开(公告)日：2016-03-17

申请号：US14488061

申请日：2014-09-16

Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE

Inventor： Cheng-Chun TU ,  Tzi-Cker CHIUEH ,  Chao-Tang LEE

IPC: G06F9/455

CPC classification number: G06F9/45558 ,  G06F2009/45575

Abstract: An interrupt handling method and a system are provided. An exemplary embodiment of an interrupt handling method in a virtualized environment operable on a computer having one or more CPU cores, includes disabling a virtual machine exit triggers by an interrupt that destined to a virtual machine (VM), via a hypervisor of the virtualized environment. The exemplary method further includes delivering directly one or more interrupts from an I/O virtualization (IOV) device and a virtual device that destined to the VM, while the destined VM is running on one of the one or more CPU cores, otherwise delivering the one or more interrupts to the hypervisor to deliver corresponding one or more virtual interrupts to the destined VM.

Abstract translation: 提供中断处理方法和系统。 在具有一个或多个CPU核心的计算机上可操作的虚拟环境中的中断处理方法的示例性实施例包括经由虚拟机环境的虚拟机管理程序禁止通过去往虚拟机（VM）的中断的虚拟机退出触发 。 该示例性方法还包括在目标VM在一个或多个CPU核之一上运行时，直接从I / O虚拟化（IOV）设备和目的地为VM的虚拟设备直接递送一个或多个中断， 对管理程序的一个或多个中断将相应的一个或多个虚拟中断传送到目的地的VM。