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公开(公告)号：US09836318B2
公开(公告)日：2017-12-05
申请号：US14206033
申请日：2014-03-12
Applicant: Infineon Technologies AG
Inventor： Simon Brewerton , Glenn Farrall , Neil Hastie , Frank Hellwig , Richard Knight , Antonio Vilela
CPC classification number: G06F9/45558 , G06F9/30043 , G06F13/28 , G06F21/71 , G06F21/85 , G06F2009/45583 , G06F2009/45587
Abstract: The disclosure relates to systems and methods for defining a processor safety privilege level for controlling a distributed memory access protection system. More specifically, a safety hypervisor function for accessing a bus in a computer processing system includes a module, such as a Computer Processing Unit (CPU) or a Direct Memory Access (DMY) for accessing a system memory and a memory unit for storing a safety code, such as a Processor Status Word (PSW) or a configuration register (DMA (REG)). The module allocates the safety code to a processing transaction and the safety code is visible upon access of the bus by the module.
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公开(公告)号：US09891917B2
公开(公告)日：2018-02-13
申请号：US13786550
申请日：2013-03-06
Applicant: Infineon Technologies AG
Inventor： Neil Hastie , Simon Brewerton
CPC classification number: G06F9/3005 , G06F11/0724 , G06F11/0793 , G06F11/1641
Abstract: A system and method for increasing lockstep core availability provides for writing a state of a main CPU core to a state buffer, executing one or more instructions of a task by the main CPU core to generate a first output for each executed instruction, and executing the one or more instructions of the task by a checker CPU core to generate a second output for each executed instruction. The method further includes comparing the first output with the second output, and if the first output does not match the second output, generating one or more control signals, and based upon the generation of the one or more control signals, loading the state of the main CPU core from the state buffer to the main CPU core and the checker CPU core.
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公开(公告)号：US20150242233A1
公开(公告)日：2015-08-27
申请号：US14206033
申请日：2014-03-12
Applicant: Infineon Technologies AG
Inventor： Simon Brewerton , Glenn Farrall , Neil Hastie , Frank Hellwig , Richard Knight , Antonio Vilela
CPC classification number: G06F9/45558 , G06F9/30043 , G06F13/28 , G06F21/71 , G06F21/85 , G06F2009/45583 , G06F2009/45587
Abstract: The disclosure relates to systems and methods for defining a processor safety privilege level for controlling a distributed memory access protection system. More specifically, a safety hypervisor function for accessing a bus in a computer processing system includes a module, such as a Computer Processing Unit (CPU) or a Direct Memory Access (DMY) for accessing a system memory and a memory unit for storing a safety code, such as a Processor Status Word (PSW) or a configuration register (DMA (REG)). The module allocates the safety code to a processing transaction and the safety code is visible upon access of the bus by the module.
Abstract translation: 本公开涉及用于定义用于控制分布式存储器访问保护系统的处理器安全特权级别的系统和方法。 更具体地，用于在计算机处理系统中访问总线的安全管理程序功能包括用于访问系统存储器的诸如计算机处理单元（CPU）或直接存储器访问（DMY）的模块以及用于存储安全性的存储单元 代码，如处理器状态字（PSW）或配置寄存器（DMA（REG））。 该模块将安全代码分配给处理事务，并且安全代码在模块访问总线时可见。
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Patent Agency Ranking
公开(公告)号：US10248595B2
公开(公告)日：2019-04-02
申请号：US15673943
申请日：2017-08-10
Applicant: Infineon Technologies AG
Inventor： Frank Hellwig , Gerhard Wirrer , Glenn Farrall , Neil Hastie
Abstract: An interrupt interface of a central processing unit (CPU) comprises a bus with a plurality of interfaces to various components of the CPU. These components can include a memory that includes instructions to execute operations of a processor component, a plurality of virtual machines (VMs) and a virtual machine monitor (VMM)/hypervisor configured to execute the plurality of VMs. The processor can receive interrupt requests (interrupt) as service requests in parallel, which can be executed by the VMM or any one or more of the plurality of VMs to execute VM applications on a dedicated instance of a guest operating system for a task. The processor can further determine whether to grant an interrupt request to the VMM and the VMs based on predetermined criteria, including a current task priority, a pending interrupt priority, or an interrupt enable, associated with the current status of each of the component.
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公开(公告)号：US20190050356A1
公开(公告)日：2019-02-14
申请号：US15673943
申请日：2017-08-10
Applicant: Infineon Technologies AG
Inventor： Frank Hellwig , Gerhard Wirrer , Glenn Farrall , Neil Hastie
Abstract: An interrupt interface of a central processing unit (CPU) comprises a bus with a plurality of interfaces to various components of the CPU. These components can include a memory that includes instructions to execute operations of a processor component, a plurality of virtual machines (VMs) and a virtual machine monitor (VMM)/hypervisor configured to execute the plurality of VMs. The processor can receive interrupt requests (interrupt) as service requests in parallel, which can be executed by the VMM or any one or more of the plurality of VMs to execute VM applications on a dedicated instance of a guest operating system for a task. The processor can further determine whether to grant an interrupt request to the VMM and the VMs based on predetermined criteria, including a current task priority, a pending interrupt priority, or an interrupt enable, associated with the current status of each of the component.
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公开(公告)号：US20180039508A1
公开(公告)日：2018-02-08
申请号：US15784528
申请日：2017-10-16
Applicant: Infineon Technologies AG
Inventor： Simon Brewerton , Glenn Farrall , Neil Hastie , Frank Hellwig , Richard Knight , Antonio Vilela
CPC classification number: G06F9/45558 , G06F9/30043 , G06F13/28 , G06F21/71 , G06F21/85 , G06F2009/45583 , G06F2009/45587
Abstract: The disclosure relates to systems and methods for defining a processor safety privilege level for controlling a distributed memory access protection system. More specifically, a safety hypervisor function for accessing a bus in a computer processing system includes a module, such as a Computer Processing Unit (CPU) or a Direct Memory Access (DMA) for accessing a system memory and a memory unit for storing a safety code, such as a Processor Status Word (PSW) or a configuration register (DMA (REG)). The module allocates the safety code to a processing transaction and the safety code is visible upon access of the bus by the module.
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公开(公告)号：US20140258684A1
公开(公告)日：2014-09-11
申请号：US13786550
申请日：2013-03-06
Applicant: INFINEON TECHNOLOGIES AG
Inventor： Neil Hastie , Simon Brewerton
IPC: G06F9/30
CPC classification number: G06F9/3005 , G06F11/0724 , G06F11/0793 , G06F11/1641
Abstract: A system and method for increasing lockstep core availability provides for writing a state of a main CPU core to a state buffer, executing one or more instructions of a task by the main CPU core to generate a first output for each executed instruction, and executing the one or more instructions of the task by a checker CPU core to generate a second output for each executed instruction. The method further includes comparing the first output with the second output, and if the first output does not match the second output, generating one or more control signals, and based upon the generation of the one or more control signals, loading the state of the main CPU core from the state buffer to the main CPU core and the checker CPU core.
Abstract translation: 用于增加锁步核心可用性的系统和方法提供将主CPU内核的状态写入状态缓冲器，由主CPU内核执行任务的一个或多个指令以为每个执行的指令生成第一输出，并且执行 一个或多个任务的指令由检验CPU核心产生用于每个执行的指令的第二输出。 该方法还包括将第一输出与第二输出进行比较，如果第一输出与第二输出不匹配，则产生一个或多个控制信号，并且基于一个或多个控制信号的产生， 主CPU内核从状态缓冲区到主CPU内核和核心CPU核心。
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公开(公告)号：US10592270B2
公开(公告)日：2020-03-17
申请号：US15784528
申请日：2017-10-16
Applicant: Infineon Technologies AG
Inventor： Simon Brewerton , Glenn Farrall , Neil Hastie , Frank Hellwig , Richard Knight , Antonio Vilela
Abstract: The disclosure relates to systems and methods for defining a processor safety privilege level for controlling a distributed memory access protection system. More specifically, a safety hypervisor function for accessing a bus in a computer processing system includes a module, such as a Computer Processing Unit (CPU) or a Direct Memory Access (DMA) for accessing a system memory and a memory unit for storing a safety code, such as a Processor Status Word (PSW) or a configuration register (DMA (REG)). The module allocates the safety code to a processing transaction and the safety code is visible upon access of the bus by the module.
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