公开(公告)号：US09165828B2

公开(公告)日：2015-10-20

申请号：US14153322

申请日：2014-01-13

Applicant: Infineon Technologies AG

Inventor： Gabriele Bettineschi ,  Uwe Seidel ,  Wolfgang Walter ,  Michael Schrenk ,  Hubert Werthmann

IPC: H01L21/768 ,  H01L23/525

CPC classification number: H01L21/76886 ,  H01L23/5256 ,  H01L2224/13

Abstract: A semiconductor device comprises a semiconductor substrate, an anorganic isolation layer on the semiconductor substrate and a metallization layer on the anorganic isolation layer. The metallization layer comprises a fuse structure. At least in an area of the fuse structure the metallization layer and the anorganic isolation layer have a common interface.

Abstract translation: 半导体器件包括半导体衬底，半导体衬底上的无机隔离层和有机隔离层上的金属化层。 金属化层包括熔丝结构。 至少在熔丝结构的区域中，金属化层和有机隔离层具有共同的界面。

公开(公告)号：US09188625B2

公开(公告)日：2015-11-17

申请号：US14098210

申请日：2013-12-05

Applicant: Infineon Technologies AG

Inventor： Wolfgang Walter ,  Klaus Koller

IPC: G01R31/26 ,  G01R31/28 ,  H01L21/66 ,  H01L23/58

CPC classification number: G01R31/2607 ,  G01R31/2858 ,  H01L22/34 ,  H01L23/585 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Semiconductor device test structures and methods are disclosed. In a preferred embodiment, a test structure includes a feed line disposed in a first conductive material layer, and a stress line disposed in the first conductive material layer proximate the feed line yet spaced apart from the feed line. The stress line is coupled to the feed line by a conductive feature disposed in at least one second conductive material layer proximate the first conductive material layer.

Abstract translation: 公开了半导体器件测试结构和方法。 在优选实施例中，测试结构包括设置在第一导电材料层中的馈电线，以及设置在第一导电材料层中的紧靠馈电线但与馈电线间隔开的应力线。 应力线通过布置在靠近第一导电材料层的至少一个第二导电材料层中的导电特征耦合到馈电线。

公开(公告)号：US20140127895A1

公开(公告)日：2014-05-08

申请号：US14153322

申请日：2014-01-13

Applicant: INFINEON TECHNOLOGIES AG

Inventor： Gabriele Bettineschi ,  Uwe Seidel ,  Wolfgang Walter ,  Michael Schrenk ,  Hubert Werthmann

IPC: H01L21/768

CPC classification number: H01L21/76886 ,  H01L23/5256 ,  H01L2224/13

Abstract: A semiconductor device comprises a semiconductor substrate, an anorganic isolation layer on the semiconductor substrate and a metallization layer on the anorganic isolation layer. The metallization layer comprises a fuse structure. At least in an area of the fuse structure the metallization layer and the anorganic isolation layer have a common interface.

Abstract translation: 半导体器件包括半导体衬底，半导体衬底上的无机隔离层和有机隔离层上的金属化层。 金属化层包括熔丝结构。 至少在熔丝结构的区域中，金属化层和有机隔离层具有共同的界面。

公开(公告)号：US20140097864A1

公开(公告)日：2014-04-10

申请号：US14098210

申请日：2013-12-05

Applicant: Infineon Technologies AG

Inventor： Wolfgang Walter ,  Klaus Koller

IPC: G01R31/26

CPC classification number: G01R31/2607 ,  G01R31/2858 ,  H01L22/34 ,  H01L23/585 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Semiconductor device test structures and methods are disclosed. In a preferred embodiment, a test structure includes a feed line disposed in a first conductive material layer, and a stress line disposed in the first conductive material layer proximate the feed line yet spaced apart from the feed line. The stress line is coupled to the feed line by a conductive feature disposed in at least one second conductive material layer proximate the first conductive material layer.

Abstract translation: 公开了半导体器件测试结构和方法。 在优选实施例中，测试结构包括设置在第一导电材料层中的馈电线，以及设置在第一导电材料层中的紧靠馈电线但与馈电线间隔开的应力线。 应力线通过布置在靠近第一导电材料层的至少一个第二导电材料层中的导电特征耦合到馈电线。