公开(公告)号：US20130328178A1

公开(公告)日：2013-12-12

申请号：US13967547

申请日：2013-08-15

Applicant: Infineon Technologies AG

Inventor： Winfried Bakalski ,  Bernd Eisener ,  Uwe Seidel ,  Markus Zannoth

IPC: H01L23/552

CPC classification number: H01L23/552 ,  H01L23/5225 ,  H01L23/60 ,  H01L2924/0002 ,  H01L2924/00

Abstract: One aspect of the invention relates to a shielding device for shielding from electromagnetic radiation, including a shielding base element, a shielding cover element and a shielding lateral element for electrically connecting the base element to the cover element in such that a circuit part to be shielded is arranged within the shielding elements. Since at least one partial section of the shielding elements includes a semiconductor material, a shielding device can be realized completely and cost-effectively in an integrated circuit.

Abstract translation: 本发明的一个方面涉及一种用于屏蔽电磁辐射的屏蔽装置，包括屏蔽基座元件，屏蔽盖元件和屏蔽横向元件，用于将基座元件电连接到覆盖元件，使屏蔽电路部分 布置在屏蔽元件内。 由于屏蔽元件的至少一部分包括半导体材料，因此可以在集成电路中完全且成本有效地实现屏蔽装置。

公开(公告)号：US11605572B2

公开(公告)日：2023-03-14

申请号：US17237143

申请日：2021-04-22

Applicant: Infineon Technologies AG

Inventor： Daniel Porwol ,  Thomas Fischer ,  Uwe Seidel ,  Anton Steltenpohl

IPC: H01L23/31 ,  H01L21/683 ,  H01L23/29 ,  H01L23/00

Abstract: An electronic component includes a mold layer and a semiconductor die including a low ohmic first portion and a high ohmic second portion. The low ohmic first portion has an active area. The high ohmic second portion is arranged on the mold layer.

公开(公告)号：US09659877B2

公开(公告)日：2017-05-23

申请号：US13967547

申请日：2013-08-15

Applicant: Infineon Technologies AG

Inventor： Winfried Bakalski ,  Bernd Eisener ,  Uwe Seidel ,  Markus Zannoth

IPC: H01L23/552 ,  H01L23/522 ,  H01L23/60

CPC classification number: H01L23/552 ,  H01L23/5225 ,  H01L23/60 ,  H01L2924/0002 ,  H01L2924/00

Abstract: One aspect of the invention relates to a shielding device for shielding from electromagnetic radiation, including a shielding base element, a shielding cover element and a shielding lateral element for electrically connecting the base element to the cover element in such that a circuit part to be shielded is arranged within the shielding elements. Since at least one partial section of the shielding elements includes a semiconductor material, a shielding device can be realized completely and cost-effectively in an integrated circuit.

公开(公告)号：US09165828B2

公开(公告)日：2015-10-20

申请号：US14153322

申请日：2014-01-13

Applicant: Infineon Technologies AG

Inventor： Gabriele Bettineschi ,  Uwe Seidel ,  Wolfgang Walter ,  Michael Schrenk ,  Hubert Werthmann

IPC: H01L21/768 ,  H01L23/525

CPC classification number: H01L21/76886 ,  H01L23/5256 ,  H01L2224/13

Abstract: A semiconductor device comprises a semiconductor substrate, an anorganic isolation layer on the semiconductor substrate and a metallization layer on the anorganic isolation layer. The metallization layer comprises a fuse structure. At least in an area of the fuse structure the metallization layer and the anorganic isolation layer have a common interface.

Abstract translation: 半导体器件包括半导体衬底，半导体衬底上的无机隔离层和有机隔离层上的金属化层。 金属化层包括熔丝结构。 至少在熔丝结构的区域中，金属化层和有机隔离层具有共同的界面。

公开(公告)号：US20230187298A1

公开(公告)日：2023-06-15

申请号：US18107800

申请日：2023-02-09

Applicant: Infineon Technologies AG

Inventor： Daniel Porwol ,  Thomas Fischer ,  Uwe Seidel ,  Anton Steltenpohl

IPC: H01L23/31

CPC classification number: H01L23/3164 ,  H01L23/3121 ,  H01L23/3135 ,  H01L23/3192 ,  H01L21/6836 ,  H01L2924/10335

Abstract: A package includes: an electronic component that includes a dielectric layer as a base and a semiconductor die attached on top of the dielectric layer, the semiconductor die having an active area with monolithically integrated circuit elements; and an encapsulant encapsulating the dielectric layer and the semiconductor die. The encapsulant is a mold compound having different material properties than the dielectric layer. A method of manufacturing package is also described.

公开(公告)号：US20210335687A1

公开(公告)日：2021-10-28

申请号：US17237143

申请日：2021-04-22

Applicant: Infineon Technologies AG

Inventor： Daniel Porwol ,  Thomas Fischer ,  Uwe Seidel ,  Anton Steltenpohl

IPC: H01L23/31

Abstract: An electronic component includes a mold layer and a semiconductor die including a low ohmic first portion and a high ohmic second portion. The low ohmic first portion has an active area. The high ohmic second portion is arranged on the mold layer.

公开(公告)号：US20130267093A1

公开(公告)日：2013-10-10

申请号：US13830185

申请日：2013-03-14

Applicant: INFINEON TECHNOLOGIES AG

Inventor： Albert Birner ,  Uwe Hoeckele ,  Thomas Kunstmann ,  Uwe Seidel

IPC: H01L21/768

CPC classification number: H01L21/76877 ,  H01L21/76898 ,  H01L23/481 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/13009 ,  H01L2224/13025 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01019 ,  H01L2924/01068 ,  H01L2924/01079 ,  H01L2924/00012 ,  H01L2224/05552

Abstract: A structure and method of forming through substrate vias in forming semiconductor components are described. In one embodiment, the invention describes a method of forming the through substrate via by filling an opening with a first fill material and depositing a first insulating layer over the first fill material, the first insulating layer not being deposited on sidewalls of the fill material in the opening, wherein sidewalls of the first insulating layer form a gap over the opening. The method further includes forming a void by sealing the opening using a second insulating layer.

Abstract translation: 描述了在形成半导体部件时通过衬底通孔形成的结构和方法。 在一个实施例中，本发明描述了一种通过用第一填充材料填充开口形成通孔基底通孔的方法，并且在第一填充材料上沉积第一绝缘层，第一绝缘层未沉积在填充材料的侧壁上 所述开口，其中所述第一绝缘层的侧壁在所述开口上形成间隙。 该方法还包括通过使用第二绝缘层密封开口来形成空隙。

公开(公告)号：US20250029884A1

公开(公告)日：2025-01-23

申请号：US18904744

申请日：2024-10-02

Applicant: Infineon Technologies AG

Inventor： Daniel Porwol ,  Thomas Fischer ,  Uwe Seidel ,  Anton Steltenpohl

IPC: H01L23/31 ,  H01L21/683 ,  H01L23/00 ,  H01L23/29

Abstract: A method of manufacturing a package that includes providing an electronic component that includes a dielectric layer as a base and a semiconductor die attached on top of the dielectric layer. The semiconductor die having an active area with monolithically integrated circuit elements. Encapsulating the dielectric layer and the semiconductor die by an encapsulant. The encapsulant is a mold compound having different material properties than the dielectric layer, and the dielectric layer includes a polymer.

公开(公告)号：US12112992B2

公开(公告)日：2024-10-08

申请号：US18107800

申请日：2023-02-09

Applicant: Infineon Technologies AG

Inventor： Daniel Porwol ,  Thomas Fischer ,  Uwe Seidel ,  Anton Steltenpohl

IPC: H01L23/31 ,  H01L21/683 ,  H01L23/29 ,  H01L23/00

CPC classification number: H01L23/3164 ,  H01L23/3121 ,  H01L23/3135 ,  H01L23/3192 ,  H01L21/6836 ,  H01L23/295 ,  H01L24/02 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L2221/68327 ,  H01L2221/68368 ,  H01L2224/02377 ,  H01L2224/02381 ,  H01L2224/05569 ,  H01L2224/13024 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2924/10252 ,  H01L2924/10253 ,  H01L2924/10254 ,  H01L2924/10272 ,  H01L2924/10329 ,  H01L2924/1033 ,  H01L2924/10335

Abstract: A package includes: an electronic component that includes a dielectric layer as a base and a semiconductor die attached on top of the dielectric layer, the semiconductor die having an active area with monolithically integrated circuit elements; and an encapsulant encapsulating the dielectric layer and the semiconductor die. The encapsulant is a mold compound having different material properties than the dielectric layer. A method of manufacturing package is also described.

公开(公告)号：US20190043716A1

公开(公告)日：2019-02-07

申请号：US16043365

申请日：2018-07-24

Applicant: Infineon Technologies AG

Inventor： Christoph Kadow ,  Uwe Seidel

IPC: H01L21/02 ,  H01L25/065 ,  H01L21/268

Abstract: A method for manufacturing a device includes: providing a semiconductor substrate having an RF-device; providing a BEOL-layer stack on the first main surface of the semiconductor substrate; attaching a carrier structure to a first main surface of the BEOL-layer stack; removing a lateral portion of the semiconductor substrate which laterally adjoins the device region to expose a lateral portion of the second main surface of the BEOL-layer stack; and opening a contacting region of the BEOL-layer stack at the lateral portion of second main surface of the BEOL-layer stack.