公开(公告)号：US20210406075A1

公开(公告)日：2021-12-30

申请号：US16914301

申请日：2020-06-27

Applicant: Intel Corporation

Inventor： RAMESHKUMAR ILLIKKAL ,  ANDREW J. HERDRICH ,  FRANCESC GUIM BERNAT ,  RAVISHANKAR IYER

IPC: G06F9/50 ,  G06F9/30 ,  G06F9/48 ,  G06F11/34 ,  G06F11/30

Abstract: An apparatus and method for dynamic resource allocation with mile/performance markers. For example, one embodiment of a processor comprises: resource allocation circuitry to allocate a plurality of hardware resources to a plurality of workloads including priority workloads associated with one or more guaranteed performance levels; and monitoring circuitry to evaluate execution progress of a workload across a plurality of nodes, each node to execute one or more processing stages of the workload, wherein the monitoring circuitry is to evaluate the execution progress of the workload, at least in part, by reading progress markers advertised by the workload at the specified processing stages, wherein the monitoring circuitry is to detect that the workload may not meet one of the guaranteed performance levels based on the progress markers, and wherein the resource allocation circuitry, responsive to the monitoring circuitry, is to reallocate one or more of the plurality of hardware resources to improve the performance level of the workload.

公开(公告)号：US20180060136A1

公开(公告)日：2018-03-01

申请号：US15676948

申请日：2017-08-14

Applicant: INTEL CORPORATION

Inventor： ANDREW J. HERDRICH ,  KAPIL SOOD ,  NRUPAL R. JANI ,  DAVID J. HARRIMAN ,  MESUT A. ERGIN ,  SCOTT P. DUBAL ,  RAVISHANKAR IYER

IPC: G06F9/50

CPC classification number: G06F9/5077

Abstract: Examples may include techniques to coordinate the sharing of resources among virtual elements, including service chains, supported by a shared pool of configurable computing resources based on relative priority among the virtual element and service chains. Information including indications of the performance of the service chains and also the relative priority of the service chains may be received. The resource allocation of portions of the shared pool of configurable computing resources supporting the service chains can be adjusted based on the received performance and priority information.

公开(公告)号：US20160299849A1

公开(公告)日：2016-10-13

申请号：US14680287

申请日：2015-04-07

Applicant: Intel Corporation

Inventor： ANDREW J. HERDRICH ,  EDWIN VERPLANKE ,  RAVISHANKAR IYER ,  CHRISTOPHER C. GIANOS ,  JEFFREY D. CHAMBERLAIN ,  RONAK SINGHAL ,  JULIUS MANDELBLAT ,  BRET L. TOLL

IPC: G06F12/08

CPC classification number: G06F12/0804 ,  G06F12/0811 ,  G06F12/084 ,  G06F12/0842 ,  G06F12/0848 ,  G06F12/0864 ,  G06F12/0875 ,  G06F12/0895 ,  G06F12/0897 ,  G06F12/123 ,  G06F12/128 ,  G06F2212/1004 ,  G06F2212/1016 ,  G06F2212/1024 ,  G06F2212/604

Abstract: Systems and methods for cache allocation with code and data prioritization. An example system may comprise: a cache; a processing core, operatively coupled to the cache; and a cache control logic, responsive to receiving a cache fill request comprising an identifier of a request type and an identifier of a class of service, to identify a subset of the cache corresponding to a capacity bit mask associated with the request type and the class of service.

Abstract translation: 具有代码和数据优先级的缓存分配的系统和方法。 示例系统可以包括：高速缓存; 处理核心，可操作地耦合到高速缓存; 以及高速缓存控制逻辑，响应于接收到包括请求类型的标识符和服务等级的标识符的高速缓存填充请求，以识别对应于与请求类型和类别相关联的容量位掩码的高速缓存的子集 的服务。