公开(公告)号：US20240078453A1

公开(公告)日：2024-03-07

申请号：US18466981

申请日：2023-09-14

Applicant: Intel Corporation

Inventor： Ajit Singh ,  Bharat Daga ,  Michael Behar

IPC: G06N5/046 ,  G06F13/10 ,  G06F13/28 ,  G06F17/16 ,  G06N3/04 ,  G06N3/08 ,  G06N20/00 ,  G06T9/00 ,  G06T15/20

CPC classification number: G06N5/046 ,  G06F13/10 ,  G06F13/28 ,  G06F17/16 ,  G06N3/04 ,  G06N3/08 ,  G06N20/00 ,  G06T9/002 ,  G06T15/205

Abstract: Embodiments described herein provide a processing apparatus comprising compute circuitry to generate neural network data for a convolutional neural network (CNN) and write the neural network data to a memory buffer. The compute circuitry additionally includes a direct memory access (DMA) controller including a hardware codec having encode circuitry and a decode circuitry. The DMA controller reads the neural network data from the memory buffer, encode the neural network data via the encode circuit, writes encoded neural network data to a memory device coupled with the processing apparatus, writes metadata for the encoded neural network data to the memory device coupled with the processing apparatus, and decodes encoded neural network data via the decode circuit in response to a request from the compute circuitry.

公开(公告)号：US12147914B2

公开(公告)日：2024-11-19

申请号：US18466981

申请日：2023-09-14

Applicant: Intel Corporation

Inventor： Ajit Singh ,  Bharat Daga ,  Michael Behar

IPC: G06F13/10 ,  G06F13/28 ,  G06F17/16 ,  G06N3/04 ,  G06N3/08 ,  G06N5/046 ,  G06N20/00 ,  G06T9/00 ,  G06T15/20

Abstract: Embodiments described herein provide a processing apparatus comprising compute circuitry to generate neural network data for a convolutional neural network (CNN) and write the neural network data to a memory buffer. The compute circuitry additionally includes a direct memory access (DMA) controller including a hardware codec having encode circuitry and a decode circuitry. The DMA controller reads the neural network data from the memory buffer, encode the neural network data via the encode circuit, writes encoded neural network data to a memory device coupled with the processing apparatus, writes metadata for the encoded neural network data to the memory device coupled with the processing apparatus, and decodes encoded neural network data via the decode circuit in response to a request from the compute circuitry.

公开(公告)号：US11763183B2

公开(公告)日：2023-09-19

申请号：US17390528

申请日：2021-07-30

Applicant: Intel Corporation

Inventor： Ajit Singh ,  Bharat Daga ,  Michael Behar

IPC: G06N3/08 ,  G06F13/10 ,  G06N3/04 ,  G06N5/046 ,  G06T15/20 ,  G06F17/16 ,  G06F13/28 ,  G06N20/00 ,  G06T9/00

CPC classification number: G06N5/046 ,  G06F13/10 ,  G06F13/28 ,  G06F17/16 ,  G06N3/04 ,  G06N3/08 ,  G06N20/00 ,  G06T9/002 ,  G06T15/205

Abstract: Embodiments described herein provide a processing apparatus comprising compute circuitry to generate neural network data for a convolutional neural network (CNN) and write the neural network data to a memory buffer. The compute circuitry additionally includes a direct memory access (DMA) controller including a hardware codec having encode circuitry and a decode circuitry. The DMA controller reads the neural network data from the memory buffer, encode the neural network data via the encode circuit, writes encoded neural network data to a memory device coupled with the processing apparatus, writes metadata for the encoded neural network data to the memory device coupled with the processing apparatus, and decodes encoded neural network data via the decode circuit in response to a request from the compute circuitry.

公开(公告)号：US20210357793A1

公开(公告)日：2021-11-18

申请号：US17390528

申请日：2021-07-30

Applicant: Intel Corporation

Inventor： Ajit Singh ,  Bharat Daga ,  Michael Behar

IPC: G06N5/04 ,  G06T15/20 ,  G06F17/16 ,  G06F13/28 ,  G06N20/00 ,  G06N3/08 ,  G06F13/10 ,  G06T9/00

Abstract: Embodiments described herein provide a processing apparatus comprising compute circuitry to generate neural network data for a convolutional neural network (CNN) and write the neural network data to a memory buffer. The compute circuitry additionally includes a direct memory access (DMA) controller including a hardware codec having encode circuitry and a decode circuitry. The DMA controller reads the neural network data from the memory buffer, encode the neural network data via the encode circuit, writes encoded neural network data to a memory device coupled with the processing apparatus, writes metadata for the encoded neural network data to the memory device coupled with the processing apparatus, and decodes encoded neural network data via the decode circuit in response to a request from the compute circuitry.

公开(公告)号：US11080611B2

公开(公告)日：2021-08-03

申请号：US15853457

申请日：2017-12-22

Applicant: Intel Corporation

Inventor： Ajit Singh ,  Bharat Daga ,  Michael Behar

IPC: G06N3/08 ,  G06F13/10 ,  G06T9/00 ,  G06N5/04 ,  G06T15/20 ,  G06F17/16 ,  G06F13/28 ,  G06N20/00

Abstract: Embodiments described herein provide a processing apparatus comprising compute logic to generate neural network data for a convolutional neural network (CNN) and write the neural network data to a memory buffer. The compute logic additionally includes a direct memory access (DMA) controller including a hardware codec having an encode unit and a decode unit, the DMA controller to read the neural network data from the memory buffer, encode the neural network data via the encode unit, write encoded neural network data to a memory device coupled with the processing apparatus, write metadata for the encoded neural network data to the memory device coupled with the processing apparatus, and decode encoded neural network data via the decode unit in response to a request from the compute logic.

公开(公告)号：US20200097799A1

公开(公告)日：2020-03-26

申请号：US16619062

申请日：2017-06-30

Applicant: Intel Corporation

Inventor： Dilin Divakar ,  Ambili Vengallur ,  Ajit Singh

IPC: G06N3/04 ,  G06N3/063 ,  G06N3/08 ,  G06F7/523

Abstract: Heterogeneous multiplier circuitry is provided with an interface to a configuration register to access configuration information, where the configuration information identifies respective data formats of a first operand and a second operand to be used in a first multiplication operation, where the first operand is in a first data format including a first numerical representation and the second operand is in a different, second data format including a different, second numerical representation. The heterogeneous multiplier circuitry includes an operand modifier to modify the second operand to generate a modified second operand, and further includes a multiplier to perform multiplication of the first operand and the modified second operand to generate a result in the first data format.

公开(公告)号：US20190066257A1

公开(公告)日：2019-02-28

申请号：US15682795

申请日：2017-08-22

Applicant: Intel Corporation

Inventor： Bharat Daga ,  Ajit Singh ,  Pradeep Janedula

IPC: G06T1/60 ,  G06T9/00

Abstract: A mechanism is described for facilitating efficient memory layout for enabling smart data compression in machine learning environments. A method of embodiments, as described herein, includes facilitating dividing an initial tile representing an image into primary multiple tiles such that each tile of the primary multiple tiles is regarded as an independent image as processed by one or more processors of a computing device. The method may further include computing the primary multiple tiles into secondary multiple tiles compatible in size of a local buffer. The method may further include merging the multiple secondary multiple tiles into a final tile representing the image, and compressing the final tile.

公开(公告)号：US10726583B2

公开(公告)日：2020-07-28

申请号：US15395495

申请日：2016-12-30

Applicant: INTEL CORPORATION

Inventor： Ajit Singh ,  Bharat Daga ,  Oren Agam ,  Michael Behar ,  Dmitri Vainbrand

IPC: G06T9/00 ,  G06N3/08 ,  G06N3/04 ,  G06F13/10 ,  G06T15/00 ,  G06T1/20

Abstract: Embodiments described herein provide a processing apparatus comprising compute logic to generate output feature map data for a convolutional neural network (CNN) and write the feature map data to a memory buffer; a direct memory access (DMA) controller including a feature map encoder, the DMA controller to read the feature map data from the memory buffer, encode the feature map data using one of multiple encode algorithms, and write encoded feature map data to memory coupled with the processing apparatus; and wherein the compute logic is to read the encoded feature map data from the memory in an encoded format and decode the encoded feature map data while reading the encoded feature map data.

公开(公告)号：US10600147B2

公开(公告)日：2020-03-24

申请号：US15682795

申请日：2017-08-22

Applicant: Intel Corporation

Inventor： Bharat Daga ,  Ajit Singh ,  Pradeep Janedula

IPC: G06K9/00 ,  G06T1/60 ,  G06T9/00 ,  G06T11/40

Abstract: A mechanism is described for facilitating efficient memory layout for enabling smart data compression in machine learning environments. A method of embodiments, as described herein, includes facilitating dividing an initial tile representing an image into primary multiple tiles such that each tile of the primary multiple tiles is regarded as an independent image as processed by one or more processors of a computing device. The method may further include computing the primary multiple tiles into secondary multiple tiles compatible in size of a local buffer. The method may further include merging the multiple secondary multiple tiles into a final tile representing the image, and compressing the final tile.

公开(公告)号：US20190197420A1

公开(公告)日：2019-06-27

申请号：US15853457

申请日：2017-12-22

Applicant: Intel Corporation

Inventor： Ajit Singh ,  Bharat Daga ,  Michael Behar

IPC: G06N5/04 ,  G06T15/20 ,  G06N99/00 ,  G06F13/28 ,  G06F17/16

CPC classification number: G06N5/046 ,  G06F13/28 ,  G06F17/16 ,  G06N20/00 ,  G06T15/205

Abstract: Embodiments described herein provide a processing apparatus comprising compute logic to generate neural network data for a convolutional neural network (CNN) and write the neural network data to a memory buffer. The compute logic additionally includes a direct memory access (DMA) controller including a hardware codec having an encode unit and a decode unit, the DMA controller to read the neural network data from the memory buffer, encode the neural network data via the encode unit, write encoded neural network data to a memory device coupled with the processing apparatus, write metadata for the encoded neural network data to the memory device coupled with the processing apparatus, and decode encoded neural network data via the decode unit in response to a request from the compute logic.