公开(公告)号：US20220027704A1

公开(公告)日：2022-01-27

申请号：US17366919

申请日：2021-07-02

Applicant: Intel Corporation

Inventor： Yonatan Glesner ,  Gal Novik ,  Dmitri Vainbrand ,  Gal Leibovich

IPC: G06N3/04 ,  G06N20/10

Abstract: Methods and apparatus relating to techniques for incremental network quantization. In an example, an apparatus comprises logic, at least partially comprising hardware logic to determine a plurality of weights for a layer of a convolutional neural network (CNN) comprising a plurality of kernels; organize the plurality of weights into a plurality of clusters for the plurality of kernels; and apply a K-means compression algorithm to each of the plurality of clusters. Other embodiments are also disclosed and claimed.

公开(公告)号：US11055604B2

公开(公告)日：2021-07-06

申请号：US15702193

申请日：2017-09-12

Applicant: Intel Corporation

Inventor： Yonatan Glesner ,  Gal Novik ,  Dmitri Vainbrand ,  Gal Leibovich

IPC: G06N3/04 ,  G06F3/06

Abstract: Methods and apparatus relating to techniques for incremental network quantization. In an example, an apparatus comprises logic, at least partially comprising hardware logic to determine a plurality of weights for a layer of a convolutional neural network (CNN) comprising a plurality of kernels; organize the plurality of weights into a plurality of clusters for the plurality of kernels; and apply a K-means compression algorithm to each of the plurality of clusters. Other embodiments are also disclosed and claimed.

公开(公告)号：US10726583B2

公开(公告)日：2020-07-28

申请号：US15395495

申请日：2016-12-30

Applicant: INTEL CORPORATION

Inventor： Ajit Singh ,  Bharat Daga ,  Oren Agam ,  Michael Behar ,  Dmitri Vainbrand

IPC: G06T9/00 ,  G06N3/08 ,  G06N3/04 ,  G06F13/10 ,  G06T15/00 ,  G06T1/20

Abstract: Embodiments described herein provide a processing apparatus comprising compute logic to generate output feature map data for a convolutional neural network (CNN) and write the feature map data to a memory buffer; a direct memory access (DMA) controller including a feature map encoder, the DMA controller to read the feature map data from the memory buffer, encode the feature map data using one of multiple encode algorithms, and write encoded feature map data to memory coupled with the processing apparatus; and wherein the compute logic is to read the encoded feature map data from the memory in an encoded format and decode the encoded feature map data while reading the encoded feature map data.

公开(公告)号：US10210137B2

公开(公告)日：2019-02-19

申请号：US15635716

申请日：2017-06-28

Applicant: Intel Corporation

Inventor： Ehud Cohen ,  Daniel David Ben-Dayan Rubin ,  Michael Behar ,  Dmitri Vainbrand

IPC: G06F17/16 ,  G06F17/17

Abstract: A processor, including: decode circuitry to decode instructions; a data cache unit including circuitry to cache data for the processor; and an approximate matrix multiplication (AMM) circuit including: a data receptor circuit to receive a weight vector w and an input vector x, both of size N, and a compression regulating parameter n; a factorizer circuit to factorize w into w≅B·s, by computing a binary factorized matrix B of size N×n, and a dictionary vector s of size n; and a binary multiplier circuit to compute w^T x≅(B·s)^T x=s^T(B^T x), the binary multiplier circuit comprising a hardware accelerator circuit to compute an array product B^T x).

公开(公告)号：US20190004997A1

公开(公告)日：2019-01-03

申请号：US15635716

申请日：2017-06-28

Applicant: Intel Corporation

Inventor： Ehud Cohen ,  Daniel David Ben-Dayan Rubin ,  Michael Behar ,  Dmitri Vainbrand

IPC: G06F17/16 ,  G06F17/17

Abstract: A processor, including: decode circuitry to decode instructions; a data cache unit including circuitry to cache data for the processor; and an approximate matrix multiplication (AMM) circuit including: a data receptor circuit to receive a weight vector w and an input vector x, both of size N, and a compression regulating parameter n; a factorizer circuit to factorize w into w≅B·s, by computing a binary factorized matrix B of size N×n, and a dictionary vector s of size n; and a binary multiplier circuit to compute w∧T x≅(B·s)∧T x=s∧T (B)∧T x), the binary multiplier circuit comprising a hardware accelerator circuit to compute an array product B∧T x).