公开(公告)号：US11665040B2

公开(公告)日：2023-05-30

申请号：US17383698

申请日：2021-07-23

Applicant: Intel Corporation

Inventor： Bernard Arambepola ,  Noam Tal ,  Sahan S. Gamage ,  Thushara Hewavithana ,  Shaul Shulman

IPC: H04W4/00 ,  H04L27/26 ,  H04L1/00 ,  H04L5/00 ,  H04L27/00

CPC classification number: H04L27/2634 ,  H04L1/004 ,  H04L1/0041 ,  H04L5/0046 ,  H04L27/0008

Abstract: Mixed mode constellation mapping to map a data block to a block of sub-carriers based on a configurable set of one or more constellation mapping schemes, and corresponding mixed mode least likelihood ratio (LLR) de-mapping based on the configurable set of one or more modulation schemes. The set may be configurable to include multiple modulation schemes to provide to a SEvSNR measure that is a non-weighted or weighted average of SEvSNR measures of the multiple modulation schemes. Mixed mode constellation mapping may be useful be configurable to control spectral efficiency versus SNR (SEvSNR) over a range of SNR with relatively fine SNR granularity, and may be configurable to control SEvSNR over a range of SNR at a fixed FEC code rate, which may include a highest available or highest permitted code rate.

公开(公告)号：US11075713B2

公开(公告)日：2021-07-27

申请号：US16714640

申请日：2019-12-13

Applicant: Intel Corporation

Inventor： Bernard Arambepola ,  Noam Tal ,  Sahan S. Gamage ,  Thushara Hewavithana ,  Shaul Shulman

IPC: H04W4/00 ,  H04L1/00 ,  H04L5/00 ,  H04L27/00 ,  H04L27/26

Abstract: Mixed mode constellation mapping to map a data block to a block of sub-carriers based on a configurable set of one or more constellation mapping schemes, and corresponding mixed mode least likelihood ratio (LLR) de-mapping based on the configurable set of one or more modulation schemes. The set may be configurable to include multiple modulation schemes to provide to a SEvSNR measure that is a non-weighted or weighted average of SEvSNR measures of the multiple modulation schemes. Mixed mode constellation mapping may be useful be configurable to control spectral efficiency versus SNR (SEvSNR) over a range of SNR with relatively fine SNR granularity, and may be configurable to control SEvSNR over a range of SNR at a fixed FEC code rate, which may include a highest available or highest permitted code rate.

公开(公告)号：US20180287660A1

公开(公告)日：2018-10-04

申请号：US15475448

申请日：2017-03-31

Applicant: Intel Corporation

Inventor： Bernard Arambepola ,  Thushara Hewavithana ,  Noam Tal ,  Shaul Shulman

IPC: H04B3/46 ,  H04B17/345

Abstract: A cable modem system for discovering interference groups (IGs) includes an infrastructure and a cable modem termination system (CMTS). The infrastructure is for transferring data. The CMTS is configured to initiate generation of test signals by a set of cable modems (CMs), obtain a set of test measurements for the set of CMs, discover interference groups (IGs) of the set of CMs based on the obtained set of test measurements and assign a plurality of upstream and downstream channels for the set of CMs that use orthogonal frequency division multiplexing (OFDM) based on the discovered IGs.

公开(公告)号：US09954708B2

公开(公告)日：2018-04-24

申请号：US14081586

申请日：2013-11-15

Applicant: Intel Corporation

Inventor： Bernard Arambepola ,  Parveen K. Shukla ,  Thushara Hewavithana ,  Sahan S. Gamage

IPC: H04L27/00 ,  H04B7/02 ,  H04L27/26 ,  G06F12/00 ,  G06F7/76

CPC classification number: H04L27/2627 ,  G06F7/768 ,  G06F12/00 ,  H03M13/271 ,  H04L1/0071 ,  H04L27/2628 ,  H04L27/263 ,  H04L27/2634

Abstract: The disclosure generally relates to a method and apparatus for frequency interleaving. Specifically, an embodiment of the disclosure relates to a communication system having one or more antennas, a radio, a memory circuit, and a processor circuit. The antennas can be used to communicate signals or to comply with different transmission protocols. The radio can be configured to send and receive radio signals. The memory can communicate with the processor circuit and contain instructions for the processor circuit to write data carriers along a plurality of rows and columns of a 2-D store in bit-reversed order and read the columns of 2-D store.

公开(公告)号：US20180048417A1

公开(公告)日：2018-02-15

申请号：US15790807

申请日：2017-10-23

Applicant: Intel Corporation

Inventor： Bernard Arambepola ,  Noam Tal ,  Sahan S. Gamage ,  Thushara Hewavithana ,  Shaul Shulman

IPC: H04L1/00 ,  H04L5/00 ,  H04L27/00 ,  H04L27/26

CPC classification number: H04L1/004 ,  H04L1/0041 ,  H04L5/0046 ,  H04L27/0008 ,  H04L27/2634

Abstract: Mixed mode constellation mapping to map a data block to a block of sub-carriers based on a configurable set of one or more constellation mapping schemes, and corresponding mixed mode least likelihood ratio (LLR) de-mapping based on the configurable set of one or more modulation schemes. The set may be configurable to include multiple modulation schemes to provide to a SEvSNR measure that is a non-weighted or weighted average of SEvSNR measures of the multiple modulation schemes. Mixed mode constellation mapping may be useful be configurable to control spectral efficiency versus SNR (SEvSNR) over a range of SNR with relatively fine SNR granularity, and may be configurable to control SEvSNR over a range of SNR at a fixed FEC code rate, which may include a highest available or highest permitted code rate.

公开(公告)号：US09288094B2

公开(公告)日：2016-03-15

申请号：US14133123

申请日：2013-12-18

Applicant: Intel Corporation

Inventor： Bernard Arambepola ,  Parveen K. Shukla ,  Thushara Hewavithana

IPC: H04L27/26 ,  H04L25/03

CPC classification number: H04L27/2646 ,  H04L5/0007 ,  H04L25/0218 ,  H04L25/022 ,  H04L25/0232 ,  H04L25/03343 ,  H04L27/2607 ,  H04L27/2613 ,  H04L27/2647 ,  H04L27/2665 ,  H04L27/2678

Abstract: One embodiment provides an apparatus. The apparatus includes an optimization module configured to determine a guard interval remainder based, at least in part on a comparison of an allowable microreflection interference level and an actual microreflection interference level; and a windowing module configured to window an OFDM (orthogonal frequency division multiplexed) symbol utilizing the guard interval remainder. The apparatus may further include a channel estimator module configured to determine a predicted channel frequency response based, at least in part, on a probing symbol; and a pre-equalizer module configured to pre-equalize the OFDM symbol based, at least in part, on the predicted channel frequency response.

Abstract translation: 一个实施例提供了一种装置。 该装置包括：优化模块，其被配置为至少部分地基于允许的微反射干扰电平与实际微反射干扰电平的比较来确定保护间隔余数; 以及窗口模块，被配置为利用所述保护间隔余数来对OFDM（正交频分复用）符号进行窗口化。 该装置还可以包括信道估计器模块，其被配置为至少部分地基于探测符号来确定预测的信道频率响应; 以及预均衡器模块，其被配置为至少部分地基于所预测的信道频率响应来预均衡所述OFDM符号。

公开(公告)号：US20140219324A1

公开(公告)日：2014-08-07

申请号：US13997706

申请日：2012-03-15

Applicant: INTEL CORPORATION

Inventor： Bernard Arambepola ,  Thushara Hewavithana

IPC: H04L27/22 ,  H04B17/00 ,  H04L27/01

CPC classification number: H04L27/22 ,  H04L25/03159 ,  H04L27/01 ,  H04L27/26 ,  H04L27/2665 ,  H04L27/2672 ,  H04L27/2675 ,  H04L27/2679 ,  H04L27/2695

Abstract: A system according to one embodiment includes a demodulator configured to receive an OFDM modulated signal over a channel, the signal including a sequence of symbols, each of the symbols including one or more pilot carriers and one or more data carriers; a time filtering and interpolation circuit coupled to the demodulator, the time filtering and interpolation circuit configured to estimate the frequency response of the channel based on time filtering and interpolation of the pilot carriers; a phase slope correction circuit configured to apply each of a plurality of phase slope corrections to the frequency response and to the data carriers; a frequency filtering and interpolation circuit configured to calculate frequency response estimates of the channel at data carrier frequencies based on frequency filtering and interpolation of the phase slope corrected frequency response; an equalization circuit configured to equalize the phase slope corrected data carriers based on the calculated frequency response estimates; an error calculation circuit configure to calculate the mean square error between the equalized data carriers and a nearest QAM constellation point; and an iterative phase slope optimization circuit configured to select the phase slope correction associated with the minimum of the mean square errors, wherein the selected phase slope resolves the cyclic ambiguity.

Abstract translation: 根据一个实施例的系统包括：解调器，被配置为通过信道接收OFDM调制信号，所述信号包括符号序列，每个符号包括一个或多个导频载波和一个或多个数据载波; 耦合到解调器的时间滤波和内插电路，所述时间滤波和内插电路被配置为基于导频载波的时间滤波和内插来估计信道的频率响应; 相位斜率校正电路，被配置为对频率响应和数据载波施加多个相位斜率校正中的每一个; 频率滤波和内插电路，被配置为基于频率滤波和相位斜率校正频率响应的内插来计算数据载波频率处的信道的频率响应估计; 均衡电路，被配置为基于所计算的频率响应估计来均衡相位斜率校正数据载波; 误差计算电路，用于计算均衡数据载波与最近的QAM星座点之间的均方误差; 以及迭代相位斜率优化电路，被配置为选择与所述均方误差的最小值相关联的相位斜率校正，其中所选择的相位斜率解决所述循环模糊度。

公开(公告)号：US11444811B2

公开(公告)日：2022-09-13

申请号：US16834032

申请日：2020-03-30

Applicant: Intel Corporation

Inventor： Bernard Arambepola ,  Thushara Hewavithana

IPC: H04L25/08 ,  H04B1/10 ,  H04L5/00 ,  H04L7/00 ,  H04L5/14 ,  H04L25/02 ,  H04L25/03

Abstract: Symbols are received on a downstream channel. A value of a channel synchronization parameter is determined based on the received symbols. An interference event on the downstream channel is detected. In response to detecting the interference event: an output signal is determined based on at least one cached value of the channel synchronization parameter, the at least one cached value being determined based on symbols received prior to and offset from the detecting of the interference event.

公开(公告)号：US20200266966A1

公开(公告)日：2020-08-20

申请号：US16866580

申请日：2020-05-05

Applicant: Intel Corporation

Inventor： David Barr ,  Bernard Arambepola

IPC: H04L5/14 ,  H04B3/32 ,  H04B3/02 ,  H04L12/28 ,  H04L29/06

Abstract: A head-end equipment associated with a communication system configured to interface with an interference group (IG) composed of two or more modems is disclosed. The head-end equipment comprises a memory configured to store a plurality of instructions; and one or more processors configured to retrieve the plurality of instructions from the memory. In some embodiments, the one or more processors, upon execution of the plurality of instructions from the memory, is configured to generate an advanced warning signal to be provided to one or more modems associated with the IG. In some embodiments, the advanced warning signal comprises an information that a select modem, different from the one or more modems, in the IG will be initiating an upstream communication in a select frequency band, as well as information on a start time and a duration of the upstream communication.

公开(公告)号：US20190182532A1

公开(公告)日：2019-06-13

申请号：US16185465

申请日：2018-11-09

Applicant: Intel Corporation

Inventor： Bernard Arambepola ,  Ziv Kfir

IPC: H04N21/426 ,  H04L27/26 ,  H04N21/61

Abstract: The disclosure generally relates to a method and system for fast channel scan for DOCSIS cable modems. The disclosed exemplary embodiments are directed to hybrid fiber coaxial (HFC) modems and may be equally applied to other type of modems both wired and wireless. The disclosed embodiments enable locating the Physical Link Layer Chanel (PLC) quickly by using a beacon channel at a designated frequency offset from the PLC.