公开(公告)号：US12019178B2

公开(公告)日：2024-06-25

申请号：US17392785

申请日：2021-08-03

Applicant: INTEL CORPORATION

Inventor： Ofer Markish ,  Ophir Shabtay ,  Thushara Hewavithana ,  Arnaud Amadjikpe ,  Shengbo Xu

IPC: G01S7/35 ,  B60W60/00 ,  G01S13/89 ,  H01Q1/32 ,  H01Q21/22

CPC classification number: G01S7/352 ,  H01Q1/3233 ,  H01Q21/22 ,  B60W60/001 ,  B60W2420/408 ,  G01S13/89

Abstract: Some demonstrative aspects include radar apparatuses, devices, systems and methods. In one example, an apparatus may include a plurality of Transmit (Tx) antennas to transmit radar Tx signals, and a plurality of Receive (Rx) antennas to receive radar Rx signals. For example, the radar Rx signals may be based on the radar Tx signals. The apparatus may be implemented, for example, as part of a radar device, for example, as part of a vehicle including the radar device. In other aspects, the apparatus may include any other additional or alternative elements and/or may be implemented as part of any other device.

公开(公告)号：US11838070B2

公开(公告)日：2023-12-05

申请号：US17905264

申请日：2020-03-30

Applicant: Intel Corporation

Inventor： Thushara Hewavithana ,  Nathan Goichberg

IPC: H04B3/38

CPC classification number: H04B3/38

Abstract: Examples relate to an amplification apparatus, device or method, to a Tap for a cable communication network comprising an amplification apparatus or device, and to a cable communication network comprising an amplification apparatus or device. The amplification apparatus comprises interface circuitry for exchanging a first version of a shared signal with a first component of the cable communication network. The shared signal is based on a frequency spectrum comprising at least a first frequency band and a second frequency band. The amplification apparatus comprises interface circuitry for exchanging a second version of the shared signal with a second component of the cable communication network. The amplification apparatus comprises amplifier circuitry configured to selectively amplify the first frequency band of the frequency spectrum of the shared signal, such that the first frequency band is amplified in the second version of the shared signal.

公开(公告)号：US11444811B2

公开(公告)日：2022-09-13

申请号：US16834032

申请日：2020-03-30

Applicant: Intel Corporation

Inventor： Bernard Arambepola ,  Thushara Hewavithana

IPC: H04L25/08 ,  H04B1/10 ,  H04L5/00 ,  H04L7/00 ,  H04L5/14 ,  H04L25/02 ,  H04L25/03

Abstract: Symbols are received on a downstream channel. A value of a channel synchronization parameter is determined based on the received symbols. An interference event on the downstream channel is detected. In response to detecting the interference event: an output signal is determined based on at least one cached value of the channel synchronization parameter, the at least one cached value being determined based on symbols received prior to and offset from the detecting of the interference event.

公开(公告)号：US20210116531A1

公开(公告)日：2021-04-22

申请号：US17133924

申请日：2020-12-24

Applicant: Intel Corporation

Inventor： Ophir Shabtay ,  Joseph Tabrikian ,  Thushara Hewavithana

IPC: G01S3/74 ,  G01S13/931 ,  G01S13/42 ,  G06K9/62

Abstract: For example, a radar processor may be configured to determine a first 1D AoA spectrum corresponding to a first dimension of an Azimuth-Elevation domain based on radar Rx data, to determine a second 1D AoA spectrum corresponding to a second dimension of the Azimuth-Elevation domain based on the radar Rx data, to detect one or more first object hypotheses in the first dimension based on the first 1D AoA spectrum, to detect one or more second object hypotheses in the second dimension based on the second 1D AoA spectrum, to determine a plurality of 2D object hypotheses corresponding to the Azimuth-Elevation domain based on the first object hypotheses and the second object hypotheses, and to generate 2D AoA information based on a 2D AoA spectrum analysis of the radar Rx data according to the plurality of 2D object hypotheses.

公开(公告)号：US10826635B2

公开(公告)日：2020-11-03

申请号：US16274645

申请日：2019-02-13

Applicant: Intel Corporation

Inventor： Nathan Goichberg ,  Shaul Shulman ,  Thushara Hewavithana

IPC: H04L5/14 ,  H04J3/06 ,  H04L25/03 ,  H04L12/28 ,  H04L5/00

Abstract: Synchronizing methods and architectures for cable modems to transmit and receive Full Duplex (FDX) resource block allocations (RBAs) using filter switching and coordinated updating of equalization coefficients. A cable modem including a block of switchable filters, an analog front end (AFE) and a PHY/MAC System on a Chip (SoC) tuner to, at least in part, provide signals to switch the switchable filters in accordance with the RBA changes and synchronize updating tuner equalizations to match filter switching in a coordinated manner by marking received data at the AFE.

公开(公告)号：US20200244505A1

公开(公告)日：2020-07-30

申请号：US16774349

申请日：2020-01-28

Applicant: Intel Corporation

Inventor： Thushara Hewavithana ,  Noam Tal ,  Boaz Kol ,  Murti Devarakonda

IPC: H04L27/26 ,  H04L27/00 ,  H04L27/38

Abstract: A modem circuit associated with a communication system is disclosed. The modem circuit comprises a symbol tracking circuit configured to track a symbol timing associated with a downstream (DS) channel associated with the modem circuit, in accordance with a timing offset estimate. In some embodiments, the timing offset estimate comprises a unified timing offset derived based on one or more external channels associated with the modem circuit that is different from the DS channel. The symbol tracking circuit is further configured to apply a sample rate correction to a DS signal associated with the DS channel, based on the timing offset estimate comprising the unified timing offset, and apply a frequency correction to the DS signal, based on a frequency offset estimate comprising a unified frequency offset derived based on the one or more external channels.

公开(公告)号：US10305714B2

公开(公告)日：2019-05-28

申请号：US15882156

申请日：2018-01-29

Applicant: Intel Corporation

Inventor： Bernard Arambepola ,  Parveen K. Shukla ,  Thushara Hewavithana ,  Sahan S. Gamage

IPC: H04L27/00 ,  H04B7/02 ,  H04L27/26 ,  G06F12/00 ,  G06F7/76 ,  H03M13/27 ,  H04L1/00

Abstract: The disclosure generally relates to a method and apparatus for frequency interleaving. Specifically, an embodiment of the disclosure relates to a communication system having one or more antennas, a radio, a memory circuit, and a processor circuit. The antennas can be used to communicate signals or to comply with different transmission protocols. The radio can be configured to send and receive radio signals. The memory can communicate with the processor circuit and contain instructions for the processor circuit to write data carriers along a plurality of rows and columns of a 2-D store in bit-reversed order and read the columns of 2-D store.

公开(公告)号：US10171272B2

公开(公告)日：2019-01-01

申请号：US15639196

申请日：2017-06-30

Applicant: Intel Corporation

Inventor： Thushara Hewavithana ,  Bernard Arambepola

IPC: H04L25/02 ,  H04L25/03 ,  H04L27/26

Abstract: An inter-carrier interference (ICI) mitigation circuit associated with an orthogonal frequency division multiplexing (OFDM) receiver is disclosed. The ICI mitigation circuit comprises an ICI cancellation circuit configured to receive an OFDM symbol associated with an OFDM signal and determine an ICI associated with one or more OFDM subcarriers within the OFDM symbol. The ICI cancellation circuit is further configured to cancel the ICI from the one or more OFDM subcarriers associated with the OFDM symbol, in order to generate a desired OFDM symbol. In some embodiments, the ICI is determined and cancelled at the ICI cancellation circuit, in accordance with a predetermined ICI mitigation algorithm.

公开(公告)号：US09742610B2

公开(公告)日：2017-08-22

申请号：US15069312

申请日：2016-03-14

Applicant: Intel Corporation

Inventor： Bernard Arambepola ,  Parveen K. Shukla ,  Thushara Hewavithana

IPC: H04L27/26 ,  H04L5/00 ,  H04L25/02 ,  H04L25/03

CPC classification number: H04L27/2646 ,  H04L5/0007 ,  H04L25/0218 ,  H04L25/022 ,  H04L25/0232 ,  H04L25/03343 ,  H04L27/2607 ,  H04L27/2613 ,  H04L27/2647 ,  H04L27/2665 ,  H04L27/2678

Abstract: One embodiment provides an apparatus. The apparatus includes an optimization module configured to determine a guard interval remainder based, at least in part on a comparison of an allowable microreflection interference level and an actual microreflection interference level; and a windowing module configured to window an OFDM (orthogonal frequency division multiplexed) symbol utilizing the guard interval remainder. The apparatus may further include a channel estimator module configured to determine a predicted channel frequency response based, at least in part, on a probing symbol; and a pre-equalizer module configured to pre-equalize the OFDM symbol based, at least in part, on the predicted channel frequency response.

公开(公告)号：US08938041B2

公开(公告)日：2015-01-20

申请号：US13718812

申请日：2012-12-18

Applicant: Intel Corporation

Inventor： Bernard Arambepola ,  Thushara Hewavithana

IPC: H04B1/10

CPC classification number: H04L27/0008 ,  H04L5/0007 ,  H04L5/0028 ,  H04L5/0062 ,  H04L27/0006 ,  H04L27/2626 ,  H04L27/362

Abstract: An apparatus may include a processor circuit, and a dynamic filter adjustment component for execution on the processor. The dynamic filter adjustment component may identify in a wideband communications signal a set of one or more interferer frequencies for one or more respective interferer channels of a set of communications channels to be filtered, select a kernel filter comprising a low pass filter having a channel width corresponding to a channel of the one or more interferer channels, and generate a co-channel interference (CCI) filter to stop the one or more interferer channels by inverting the kernel filter. Other embodiments are described and claimed.

Abstract translation: 设备可以包括处理器电路和用于在处理器上执行的动态滤波器调整组件。 动态滤波器调整组件可以在宽带通信信号中识别要被滤波的一组通信信道中的一个或多个相应干扰信道的一个或多个干扰信号频率的集合，选择包括低通滤波器的核心滤波器，该低通滤波器具有信道宽度 对应于一个或多个干扰信道的信道，并且产生同信道干扰（CCI）滤波器，以通过反转内核滤波器来停止一个或多个干扰信道。 描述和要求保护其他实施例。