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公开(公告)号：US12135968B2
公开(公告)日：2024-11-05
申请号：US17134358
申请日：2020-12-26
Applicant: Intel Corporation
Inventor： Alexander Heinecke , Naveen Mellempudi , Robert Valentine , Mark Charney , Christopher Hughes , Evangelos Georganas , Zeev Sperber , Amit Gradstein , Simon Rubanovich
Abstract: Techniques for converting FP16 to BF8 using bias are described. An exemplary embodiment utilizes decoder circuitry to decode a single instruction, the single instruction to include one or more fields to identify a first source operand, one or more fields to identify a second source operand, one or more fields to identify a source/destination operand, and one or more fields for an opcode, wherein the opcode is to indicate that execution circuitry is to convert packed half-precision data from the identified first and second sources to packed bfloat8 data using bias terms from the identified source/destination operand and store the packed bfloat8 data into corresponding data element positions of the identified source/destination operand; and execution circuitry to execute the decoded instruction according to the opcode to convert packed half-precision data from the identified first and second sources to packed bfloat8 data using bias terms from the identified source/destination operand and store the packed bfloat8 data into corresponding data element positions of the identified source/destination operand.
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公开(公告)号：US20220206743A1
公开(公告)日：2022-06-30
申请号：US17134358
申请日：2020-12-26
Applicant: Intel Corporation
Inventor： Alexander Heinecke , Naveen Mellempudi , Robert Valentine , Mark Charney , Christopher Hughes , Evangelos Georganas , Zeev Sperber , Amit Gradstein , Simon Rubanovich
IPC: G06F5/00
Abstract: Techniques for converting FP16 to BF8 using bias are described. An exemplary embodiment utilizes decoder circuitry to decode a single instruction, the single instruction to include one or more fields to identify a first source operand, one or more fields to identify a second source operand, one or more fields to identify a source/destination operand, and one or more fields for an opcode, wherein the opcode is to indicate that execution circuitry is to convert packed half-precision data from the identified first and second sources to packed bfloat8 data using bias terms from the identified source/destination operand and store the packed bfloat8 data into corresponding data element positions of the identified source/destination operand; and execution circuitry to execute the decoded instruction according to the opcode to convert packed half-precision data from the identified first and second sources to packed bfloat8 data using bias terms from the identified source/destination operand and store the packed bfloat8 data into corresponding data element positions of the identified source/destination operand.
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公开(公告)号：US20240248720A1
公开(公告)日：2024-07-25
申请号：US18627907
申请日：2024-04-05
Applicant: Intel Corporation
Inventor： Alexander Heinecke , Naveen Mellempudi , Robert Valentine , Mark Charney , Christopher Hughes , Evangelos Georganas , Zeev Sperber , Amit Gradstein , Simon Rubanovich
CPC classification number: G06F9/30145 , G06F7/49947 , G06F9/30025 , G06F9/30036 , H03M7/24
Abstract: Techniques for converting FP16 data elements to BF8 data elements using a single instruction are described. An exemplary apparatus includes decoder circuitry to decode a single instruction, the single instruction to include a one or more fields to identify a source operand, one or more fields to identify a destination operand, and one or more fields for an opcode, the opcode to indicate that execution circuitry is to convert packed half-precision floating-point data from the identified source to packed bfloat8 data and store the packed bfloat8 data into corresponding data element positions of the identified destination operand; and execution circuitry to execute the decoded instruction according to the opcode to convert packed half-precision floating-point data from the identified source to packed bfloat8 data and store the packed bfloat8 data into corresponding data element positions.
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4.发明公开公开(公告)号：US20240045691A1
公开(公告)日：2024-02-08
申请号：US17958374
申请日：2022-10-01
Applicant: Intel Corporation
Inventor： Naveen Mellempudi , Menachem Adelman , Evangelos Georganas , Amit Gradstein , Christopher Hughes , Alexander Heinecke , Simon Rubanovich , Uri Sherman , Zeev Sperber
CPC classification number: G06F9/3802 , G06F7/4876 , G06F17/16 , G06F9/3001
Abstract: Systems, methods, and apparatuses relating to 8-bit floating-point matrix dot product instructions are described. A processor embodiment includes fetch circuitry to fetch an instruction having fields to specify an opcode and locations of a destination matrix having single-precision elements, a first source matrix, and a second source matrix, the source matrices having elements that each comprise a quadruple of 8-bit floating-point values, the opcode to indicate execution circuitry is to cause, for each element of the first source matrix and corresponding element of the second source matrix, a conversion of the 8-bit floating-point values to single-precision values, a multiplication of different pairs of converted single-precision values to generate plurality of results, and an accumulation of the results with previous contents of a corresponding element of the destination matrix, decode circuitry to decode the fetched instruction, and the execution circuitry to respond to the decoded instruction as specified by the opcode.
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公开(公告)号：US20240045687A1
公开(公告)日：2024-02-08
申请号：US17958365
申请日：2022-10-01
Applicant: Intel Corporation
Inventor： Alexander Heinecke , Menachem Adelman , Evangelos Georganas , Amit Gradstein , Christopher Hughes , Naveen Mellempudi , Simon Rubanovich , Uri Sherman , Zeev Sperber
IPC: G06F9/30
CPC classification number: G06F9/3016 , G06F9/3013
Abstract: Techniques for FP8 classification or manipulation using single instructions are described. An exemplary instruction includes fields for an opcode, an identification of a location of a packed data source operand, an indication of one or more classification checks to perform, and an identification of a packed data destination operand, wherein the opcode is to indicate that execution circuitry is to perform, for each data element position of the packed data source operand, a classification according to the indicated one or more classification checks and store a result of the classification in a corresponding data element position of the destination operand.
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Patent Agency Ranking
公开(公告)号：US20240045682A1
公开(公告)日：2024-02-08
申请号：US17958370
申请日：2022-10-01
Applicant: Intel Corporation
Inventor： Alexander Heinecke , Menachem Adelman , Evangelos Georganas , Amit Gradstein , Christopher Hughes , Naveen Mellempudi , Simon Rubanovich , Uri Sherman , Zeev Sperber
IPC: G06F9/30
CPC classification number: G06F9/30145 , G06F9/30036 , G06F9/3001
Abstract: Techniques for scale and reduction of FP8 data elements are described. An exemplary instruction includes fields for an having fields for an opcode, an identification of a location of a first packed data source operand, an identification of a location of a second packed data source operand, and an identification of a packed data destination operand, wherein the opcode is to indicate that execution circuitry is to perform, for each data element position of the packed data source operands, a floating point scale operation of a FP8 data element of the first packed data source by multiplying the data element by a power of 2 value, wherein a value of the exponent of the power of 2 value is a floor value of a FP8 data element of the second packed data source, and store a result of the floating point scale operation into a corresponding data element position of the packed data destination operand.
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7.发明授权公开(公告)号：US09678750B2
公开(公告)日：2017-06-13
申请号：US13795234
申请日：2013-03-12
Applicant: Intel Corporation
Inventor： Mikhail Smelyanskiy , Victor Lee , Christopher Hughes , Daehyun Kim , Yen-Kuang Chen , Changkyu Kim , Jatin Chhugani , Anthony D. Nguyen , Sanjeev Kumar
CPC classification number: G06F9/30036 , G06F9/30018 , G06F9/30021 , G06F9/30032 , G06F9/3004 , G06F9/30043 , G06F9/30087 , G06F9/3834 , G06F9/3885 , G06K9/6212 , G06T5/40 , H04N1/4074
Abstract: In one embodiment, a processor may include a vector unit to perform operations on multiple data elements responsive to a single instruction, and a control unit coupled to the vector unit to provide the data elements to the vector unit, where the control unit is to enable an atomic vector operation to be performed on at least some of the data elements responsive to a first vector instruction to be executed under a first mask and a second vector instruction to be executed under a second mask. Other embodiments are described and claimed.
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8.发明授权Read and write masks update instruction for vectorization of recursive computations over interdependent data 有权读写掩码更新指令，用于通过相互依赖的数据向量化递归计算公开(公告)号：US09400650B2
公开(公告)日：2016-07-26
申请号：US13630247
申请日：2012-09-28
Applicant: Intel Corporation
Inventor： Mikhail Plotnikov , Andrey Naraikin , Christopher Hughes
IPC: G06F9/30
CPC classification number: G06F9/30036 , G06F9/30018 , G06F9/30032 , G06F9/3013
Abstract: A processor executes a mask update instruction to perform updates to a first mask register and a second mask register. A register file within the processor includes the first mask register and the second mask register. The processor includes execution circuitry to execute the mask update instruction. In response to the mask update instruction, the execution circuitry is to invert a given number of mask bits in the first mask register, and also to invert the given number of mask bits in the second mask register.
Abstract translation: 处理器执行掩码更新指令以对第一屏蔽寄存器和第二掩码寄存器执行更新。 处理器内的寄存器文件包括第一掩码寄存器和第二掩码寄存器。 处理器包括执行掩膜更新指令的执行电路。 响应于掩码更新指令，执行电路将反转第一掩码寄存器中给定数量的掩码位，并且还反转第二掩码寄存器中给定数量的掩码位。
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公开(公告)号：US20240045688A1
公开(公告)日：2024-02-08
申请号：US17958369
申请日：2022-10-01
Applicant: Intel Corporation
Inventor： Alexander Heinecke , Menachem Adelman , Evangelos Georganas , Amit Gradstein , Christopher Hughes , Naveen Mellempudi , Simon Rubanovich , Uri Sherman , Zeev Sperber
CPC classification number: G06F9/3016 , G06F7/4876 , G06F9/3001
Abstract: Techniques for performing FP8 FMA in response to an instruction are described. In some examples, an instruction has fields for an opcode, an identification of location of a packed data source/destination operand (a first source), an identification of a location of a second packed data source operand, an identification of a location of a third packed data source operand, and an identification of location of a packed data source/destination operand, wherein the opcode is to indicate operand ordering and that execution circuitry is to, per data element position, perform a FP8 value fused multiply-accumulate operation using the first, second, and third source operands and store a result in a corresponding data element position of the source/destination operand, wherein the FP8 value has an 8-bit floating point format that comprises one bit for a sign, at least 4 bits for an exponent, and at least two bits for a fraction.
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公开(公告)号：US20240045686A1
公开(公告)日：2024-02-08
申请号：US17958382
申请日：2022-10-01
Applicant: Intel Corporation
Inventor： Alexander Heinecke , Menachem Adelman , Evangelos Georganas , Amit Gradstein , Christopher Hughes , Naveen Mellempudi , Simon Rubanovich , Uri Sherman , Zeev Sperber
IPC: G06F9/30
CPC classification number: G06F9/30145 , G06F9/30025
Abstract: Techniques for converting FP8 data elements to FP16 or FP32 data elements using a single instruction are described. An example apparatus includes decoder circuitry to decode a single instruction, the single instruction to indicate that execution circuitry is to convert packed FP8 data from the identified source to packed half-precision floating-point data or single-precision floating point data and store the packed half-precision floating-point data or single-precision floating point data into corresponding data element positions of the identified destination operand.
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