公开(公告)号：US20220011939A1

公开(公告)日：2022-01-13

申请号：US17484296

申请日：2021-09-24

Applicant: Intel Corporation

Inventor： Nishant Singh ,  Daniel W. Liu ,  Sharada Venkateswaran

IPC: G06F3/06 ,  G06F11/07

Abstract: Technologies for memory mirroring across an interconnect are disclosed. In the illustrative embodiment, a primary memory agent that controls a single memory channel can implement memory mirroring by sending mirrored memory operations to a secondary memory agent over an interconnect. In the illustrative embodiment, the secondary memory agent may not be aware that it is performing mirrored memory operations. The primary memory agent may handle error recovery, scrubbing, and failover to the secondary memory agent.

公开(公告)号：US10198354B2

公开(公告)日：2019-02-05

申请号：US15465513

申请日：2017-03-21

Applicant: INTEL CORPORATION

Inventor： Wei Chen ,  Rajat Agarwal ,  Jing Ling ,  Daniel W. Liu

IPC: G06F12/06 ,  G06F12/08 ,  G06F3/06 ,  G06F12/0808 ,  G06F12/0811 ,  G06F12/128 ,  G06F12/0868

Abstract: Provided are an apparatus, system, and method to flush modified data from a first memory to a persistent second memory. A first memory controller coupled to the first memory includes at least one RAS controller to read a range of addresses in the first memory. In response to receiving a command from the power control unit, the at least one RAS controller is invoked to read data from at least one range of addresses specified for the RAS controller from the first memory. A second memory controller transfers data read from the first memory determined to be modified to the second memory. The first memory controller sends a signal to the power control unit to indicate that the modified data in the range of addresses specified for the RAS controller was flushed to the second memory in response to the RAS controller completing reading the range of addresses.

公开(公告)号：US11036634B2

公开(公告)日：2021-06-15

申请号：US16258486

申请日：2019-01-25

Applicant: INTEL CORPORATION

Inventor： Wei Chen ,  Rajat Agarwal ,  Jing Ling ,  Daniel W. Liu

IPC: G06F12/0808 ,  G06F12/0866 ,  G06F1/3287 ,  G06F3/06 ,  G06F12/06 ,  G06F12/0811 ,  G06F12/0868 ,  G06F12/128 ,  G06F12/12

Abstract: Provided are an apparatus, system, and method to flush modified data from a first memory to a persistent second memory. A first memory controller coupled to the first memory includes at least one RAS controller to read a range of addresses in the first memory. In response to receiving a command from the power control unit, the at least one RAS controller is invoked to read data from at least one range of addresses specified for the RAS controller from the first memory. A second memory controller transfers data read from the first memory determined to be modified to the second memory. The first memory controller sends a signal to the power control unit to indicate that the modified data in the range of addresses specified for the RAS controller was flushed to the second memory in response to the RAS controller completing reading the range of addresses.