中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

10 records (took 0.014 seconds)

    ACCESSING A MEMORY USING INDEX OFFSET INFORMATION
    1.
    发明公开
    ACCESSING A MEMORY USING INDEX OFFSET INFORMATION 审中-公开

    公开(公告)号：US20230195616A1

    公开(公告)日：2023-06-22

    申请号：US17553458

    申请日：2021-12-16

    Applicant: Intel Corporation

    Inventor： Monam Agarwal ,  Anand K. Enamandram ,  Wei Chen ,  Kerry Vander Kamp ,  Robert A. Branch ,  Yen-Cheng Liu

    IPC: G06F13/16 ,  G06F12/02

    CPC classification number: G06F13/161 ,  G06F12/0238 ,  G06F12/0292 ,  G06F13/1642 ,  G06F13/1668 ,  G06F2212/1021

    Abstract: Techniques and mechanisms for identifying a memory access resource which is to be a target of an access request. In an embodiment, a processor comprises route tables which are to provide entries corresponding to different respective memory access resources which are coupled to the processor. The processor further comprises a list of items which each correspond to a different respective range of addresses, wherein the items each include an identifier of a respective route table, and an identifier of a respective index offset. Based on an address of the access request, a decoder circuit of the processor searches the list to identify a corresponding one of the items. In another embodiment, the decoder circuit accesses a route table entry, based on the search, to determine how the access request is to be directed to a particular memory access resource.

    Adaptively controlling low power mode operation for a cache memory
    6.
    发明授权
    Adaptively controlling low power mode operation for a cache memory 有权
    自适应地控制高速缓冲存储器的低功耗模式操作

    公开(公告)号：US09335814B2

    公开(公告)日：2016-05-10

    申请号：US14012362

    申请日：2013-08-28

    Applicant: Intel Corporation

    Inventor： Stefan Rusu ,  Min Huang ,  Wei Chen ,  Krishnakanth V. Sistla

    IPC: G06F1/32 ,  G06F1/00 ,  G06F13/00

    CPC classification number: G06F1/3275 ,  G06F2212/1028 ,  G06F2212/601 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D50/20

    Abstract: In an embodiment, a processor includes a plurality of cores each to independently execute instructions, a cache memory including a plurality of portions distributed across a die of the processor, a plurality of sleep circuits each coupled to one of the portions of the cache memory, and at least one sleep control logic coupled to the cache memory portions to dynamically determine a sleep setting independently for each of the sleep circuits and to enable the corresponding sleep circuit to maintain the corresponding cache memory portion at a retention voltage. Other embodiments are described and claimed.

    Abstract translation: 在一个实施例中，处理器包括多个核心，每个核心各自独立地执行指令;高速缓存存储器，包括分布在处理器的管芯上的多个部分;多个休眠电路，每个休眠电路分别耦合到高速缓冲存储器的一个部分， 以及耦合到所述高速缓存存储器部分的至少一个睡眠控制逻辑，以针对每个所述睡眠电路独立动态地确定睡眠设置，并且使所述相应的休眠电路能够将所述对应的高速缓冲存储器部分维持在保持电压。 描述和要求保护其他实施例。

    Accessing a memory using index offset information
    7.
    发明授权
    Accessing a memory using index offset information 有权

    公开(公告)号：US11860670B2

    公开(公告)日：2024-01-02

    申请号：US17553458

    申请日：2021-12-16

    Applicant: Intel Corporation

    Inventor： Monam Agarwal ,  Anand K. Enamandram ,  Wei Chen ,  Kerry Vander Kamp ,  Robert A. Branch ,  Yen-Cheng Liu

    IPC: G06F12/02 ,  G06F13/16

    CPC classification number: G06F12/0292 ,  G06F12/0238 ,  G06F13/161 ,  G06F13/1642 ,  G06F13/1668 ,  G06F2212/1021

    Abstract: Techniques and mechanisms for identifying a memory access resource which is to be a target of an access request. In an embodiment, a processor comprises route tables which are to provide entries corresponding to different respective memory access resources which are coupled to the processor. The processor further comprises a list of items which each correspond to a different respective range of addresses, wherein the items each include an identifier of a respective route table, and an identifier of a respective index offset. Based on an address of the access request, a decoder circuit of the processor searches the list to identify a corresponding one of the items. In another embodiment, the decoder circuit accesses a route table entry, based on the search, to determine how the access request is to be directed to a particular memory access resource.

    Apparatus, system, and method to flush modified data from a volatile memory to a persistent second memory
    10.
    发明授权
    Apparatus, system, and method to flush modified data from a volatile memory to a persistent second memory 有权

    公开(公告)号：US10198354B2

    公开(公告)日：2019-02-05

    申请号：US15465513

    申请日：2017-03-21

    Applicant: INTEL CORPORATION

    Inventor： Wei Chen ,  Rajat Agarwal ,  Jing Ling ,  Daniel W. Liu

    IPC: G06F12/06 ,  G06F12/08 ,  G06F3/06 ,  G06F12/0808 ,  G06F12/0811 ,  G06F12/128 ,  G06F12/0868

    Abstract: Provided are an apparatus, system, and method to flush modified data from a first memory to a persistent second memory. A first memory controller coupled to the first memory includes at least one RAS controller to read a range of addresses in the first memory. In response to receiving a command from the power control unit, the at least one RAS controller is invoked to read data from at least one range of addresses specified for the RAS controller from the first memory. A second memory controller transfers data read from the first memory determined to be modified to the second memory. The first memory controller sends a signal to the power control unit to indicate that the modified data in the range of addresses specified for the RAS controller was flushed to the second memory in response to the RAS controller completing reading the range of addresses.

Patent Agency Ranking