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    Processor to perform a bit range isolation instruction
    1.
    发明授权
    Processor to perform a bit range isolation instruction 有权

    公开(公告)号：US10656947B2

    公开(公告)日：2020-05-19

    申请号：US15921134

    申请日：2018-03-14

    Applicant: Intel Corporation

    Inventor： Maxim Loktyukhin ,  Eric W. Mahurin ,  Bret L. Toll ,  Martin G. Dixon ,  Sean P. Mirkes ,  David L. Kreitzer ,  Elmoustapha Ould-Ahmed-Vall ,  Vinodh Gopal

    IPC: G06F9/30 ,  G06F9/38

    Abstract: Receiving an instruction indicating a source operand and a destination operand. Storing a result in the destination operand in response to the instruction. The result operand may have: (1) first range of bits having a first end explicitly specified by the instruction in which each bit is identical in value to a bit of the source operand in a corresponding position; and (2) second range of bits that all have a same value regardless of values of bits of the source operand in corresponding positions. Execution of instruction may complete without moving the first range of the result relative to the bits of identical value in the corresponding positions of the source operand, regardless of the location of the first range of bits in the result. Execution units to execute such instructions, computer systems having processors to execute such instructions, and machine-readable medium storing such an instruction are also disclosed.

    METHODS AND APPARATUS TO ELIMINATE PARTIAL-REDUNDANT VECTOR LOADS
    3.
    发明申请
    METHODS AND APPARATUS TO ELIMINATE PARTIAL-REDUNDANT VECTOR LOADS 有权
    消除部分冗余矢量负载的方法和装置

    公开(公告)号：US20160259628A1

    公开(公告)日：2016-09-08

    申请号：US14741160

    申请日：2015-06-16

    Applicant: Intel Corporation

    Inventor： Farhana Aleen Schuchman ,  David L. Kreitzer ,  Rakesh Krishnaiyer ,  Vyacheslav Pavlovich Zakharin ,  Sergey Preis ,  Leonardo Jose Borges ,  Philippe Thierry

    IPC: G06F9/44 ,  G06F11/36

    CPC classification number: G06F8/30 ,  G06F8/4441 ,  G06F8/452 ,  G06F11/3688

    Abstract: Methods, apparatus, systems and articles of manufacture are disclosed to eliminate partial-redundant vector loads. An example apparatus includes a node group to associate a vector operation with a node group based on a load type of the vector operation. The example apparatus also includes a candidate identifier to identify a candidate in the node group, the candidate to include a subset of vector operations of the node group. The example apparatus also includes a code optimizer to determine replacement code based on a characteristic of the candidate, and to compare an estimated cost associated with executing the replacement code to a threshold cost relative to a cost of executing the candidate. The example apparatus also includes a code generator to generate machine code using the replacement code when the estimated cost of executing the replacement code satisfies the threshold cost.

    Abstract translation: 公开了方法，装置，系统和制品以消除部分冗余矢量载荷。 示例性装置包括基于向量操作的负载类型将向量操作与节点组相关联的节点组。 示例性装置还包括用于标识节点组中的候选的候选标识符，候选者包括节点组的向量操作的子集。 示例性装置还包括代码优化器，用于基于候选者的特征来确定替换代码，并且将与执行替换代码相关联的估计成本与执行候选的成本相比较的阈值成本进行比较。 示例性装置还包括代码生成器，当执行替换代码的估计成本满足阈值成本时，使用替换代码生成机器代码。

    HAND HELD DEVICE TO PERFORM A BIT RANGE ISOLATION INSTRUCTION
    5.
    发明申请
    HAND HELD DEVICE TO PERFORM A BIT RANGE ISOLATION INSTRUCTION 审中-公开
    手持式设备执行双向隔离指令

    公开(公告)号：US20150143084A1

    公开(公告)日：2015-05-21

    申请号：US14568812

    申请日：2014-12-12

    Applicant: INTEL CORPORATION

    Inventor： Maxim Loktyukhin ,  Eric W. Mahurin ,  Bret L. Toll ,  Martin G. Dixon ,  Sean P. Mirkes ,  David L. Kreitzer ,  ELMOUSTAPHA OULD-AHMED-VALL ,  Vinodh Gopal

    IPC: G06F9/30 ,  G06F9/38

    CPC classification number: G06F9/30145 ,  G06F9/30018 ,  G06F9/30029 ,  G06F9/30094 ,  G06F9/3802

    Abstract: Receiving an instruction indicating a source operand and a destination operand. Storing a result in the destination operand in response to the instruction. The result operand may have: (1) first range of bits having a first end explicitly specified by the instruction in which each bit is identical in value to a bit of the source operand in a corresponding position; and (2) second range of bits that all have a same value regardless of values of bits of the source operand in corresponding positions. Execution of instruction may complete without moving the first range of the result relative to the bits of identical value in the corresponding positions of the source operand, regardless of the location of the first range of bits in the result. Execution units to execute such instructions, computer systems having processors to execute such instructions, and machine-readable medium storing such an instruction are also disclosed.

    Abstract translation: 接收指示源操作数和目标操作数的指令。 将结果存储在目标操作数中以响应指令。 结果操作数可以具有：（1）具有第一端的第一范围，其中每个位在相应位置中的每个位与源操作数的位相同的指令明确地指定; 和（2）与相应位置中的源操作数的位的值无关的所有位都具有相同值的第二范围。 不管移动第一范围的结果相对于源操作数的相应位置中相同值的位，执行指令都可以完成，而不考虑结果中第一个位的位置。 还公开了执行这些指令的执行单元，具有执行这种指令的处理器的计算机系统以及存储这种指令的机器可读介质。

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