公开(公告)号：US12135780B2

公开(公告)日：2024-11-05

申请号：US18232810

申请日：2023-08-10

Applicant: Intel Corporation

Inventor： Vedvyas Shanbhogue ,  Jason W. Brandt ,  Ravi L. Sahita ,  Barry E. Huntley ,  Baiju V. Patel ,  Deepak K. Gupta

IPC: G06F21/52 ,  G06F3/06 ,  G06F9/30 ,  G06F9/46 ,  G06F12/14

Abstract: A processor implementing techniques for processor extensions to protect stacks during ring transitions is provided. In one embodiment, the processor includes a plurality of registers and a processor core, operatively coupled to the plurality of registers. The plurality of registers is used to store data used in privilege level transitions. Each register of the plurality of registers is associated with a privilege level. An indicator to change a first privilege level of a currently active application to a second privilege level is received. In view of the second privilege level, a shadow stack pointer (SSP) stored in a register of the plurality of registers is selected. The register is associated with the second privilege level. By using the SSP, a shadow stack for use by the processor at the second privilege level is identified.

公开(公告)号：US20240078111A1

公开(公告)日：2024-03-07

申请号：US18324788

申请日：2023-05-26

Applicant: Intel Corporation

Inventor： Vedvyas Shanbhogue ,  Jason W. Brandt ,  Ravi L. Sahita ,  Barry E. Huntley ,  Baiju V. Patel ,  Deepak K. Gupta

IPC: G06F9/30 ,  G06F9/46 ,  G06F21/52

CPC classification number: G06F9/3004 ,  G06F9/30134 ,  G06F9/461 ,  G06F21/52

Abstract: Methods and apparatuses relating to switching of a shadow stack pointer are described. In one embodiment, a hardware processor includes a hardware decode unit to decode an instruction, and a hardware execution unit to execute the instruction to: pop a token for a thread from a shadow stack, wherein the token includes a shadow stack pointer for the thread with at least one least significant bit (LSB) of the shadow stack pointer overwritten with a bit value of an operating mode of the hardware processor for the thread, remove the bit value in the at least one LSB from the token to generate the shadow stack pointer, and set a current shadow stack pointer to the shadow stack pointer from the token when the operating mode from the token matches a current operating mode of the hardware processor.

公开(公告)号：US20170228535A1

公开(公告)日：2017-08-10

申请号：US15016068

申请日：2016-02-04

Applicant: INTEL CORPORATION

Inventor： Vedvyas Shanbhogue ,  Jason W. Brandt ,  Ravi L. Sahita ,  Barry E. Huntley ,  Baiju V. Patel ,  Deepak K. Gupta

IPC: G06F21/52 ,  G06F12/14 ,  G06F3/06

CPC classification number: G06F21/52 ,  G06F9/30101 ,  G06F9/30134 ,  G06F9/461 ,  G06F12/1491 ,  G06F2212/1052 ,  G06F2221/033 ,  G06F2221/2141

Abstract: A processor implementing techniques for processor extensions to protect stacks during ring transitions is provided. In one embodiment, the processor includes a plurality of registers and a processor core, operatively coupled to the plurality of registers. The plurality of registers is used to store data used in privilege level transitions. Each register of the plurality of registers is associated with a privilege level. An indicator to change a first privilege level of a currently active application to a second privilege level is received. In view of the second privilege level, a shadow stack pointer (SSP) stored in a register of the plurality of registers is selected. The register is associated with the second privilege level. By using the SSP, a shadow stack for use by the processor at the second privilege level is identified.

公开(公告)号：US20170185803A1

公开(公告)日：2017-06-29

申请号：US14757964

申请日：2015-12-23

Applicant: Intel Corporation

Inventor： Vedvyas Shanbhogue ,  Ravi L. Sahita ,  Deepak K. Gupta

IPC: G06F21/64 ,  G06F9/38 ,  G06F9/30

CPC classification number: G06F9/3861 ,  G06F9/3005 ,  G06F9/30054 ,  G06F9/30076 ,  G06F21/123 ,  G06F21/125

Abstract: A processor includes an execution unit and a processing logic operatively coupled to the execution unit, the processing logic to: enter a first execution state; responsive to executing a control transfer instruction having a pre-defined subcode, remain in the first execution state; responsive to executing a control transfer instruction not having the pre-defined subcode, transition into a second execution state; and responsive to determining, in the second execution state, that a next instruction to be executed differs from an ENDBRANCH instruction, raise an execution exception.

公开(公告)号：US12236243B2

公开(公告)日：2025-02-25

申请号：US18138591

申请日：2023-04-24

Applicant: Intel Corporation

Inventor： Jason W. Brandt ,  Deepak K. Gupta ,  Rodrigo Branco ,  Joseph Nuzman ,  Robert S. Chappell ,  Sergiu Ghetie ,  Wojciech Powiertowski ,  Jared W. Stark, IV ,  Ariel Sabba ,  Scott J. Cape ,  Hisham Shafi ,  Lihu Rappoport ,  Yair Berger ,  Scott P. Bobholz ,  Gilad Holzstein ,  Sagar V. Dalvi ,  Yogesh Bijlani

IPC: G06F9/38 ,  G06F9/30

Abstract: Methods and apparatuses relating to mitigations for speculative execution side channels are described. Speculative execution hardware and environments that utilize the mitigations are also described. For example, three indirect branch control mechanisms and their associated hardware are discussed herein: (i) indirect branch restricted speculation (IBRS) to restrict speculation of indirect branches, (ii) single thread indirect branch predictors (STIBP) to prevent indirect branch predictions from being controlled by a sibling thread, and (iii) indirect branch predictor barrier (IBPB) to prevent indirect branch predictions after the barrier from being controlled by software executed before the barrier.

公开(公告)号：US11762982B2

公开(公告)日：2023-09-19

申请号：US17407035

申请日：2021-08-19

Applicant: Intel Corporation

Inventor： Vedvyas Shanbhogue ,  Jason W. Brandt ,  Ravi L. Sahita ,  Barry E. Huntley ,  Baiju V. Patel ,  Deepak K. Gupta

IPC: G06F21/52 ,  G06F3/06 ,  G06F12/14 ,  G06F9/30 ,  G06F9/46

CPC classification number: G06F21/52 ,  G06F3/0622 ,  G06F3/0637 ,  G06F3/0673 ,  G06F9/30101 ,  G06F9/30134 ,  G06F9/461 ,  G06F12/1491 ,  G06F2212/1052 ,  G06F2221/033 ,  G06F2221/2141

Abstract: A processor implementing techniques for processor extensions to protect stacks during ring transitions is provided. In one embodiment, the processor includes a plurality of registers and a processor core, operatively coupled to the plurality of registers. The plurality of registers is used to store data used in privilege level transitions. Each register of the plurality of registers is associated with a privilege level. An indicator to change a first privilege level of a currently active application to a second privilege level is received. In view of the second privilege level, a shadow stack pointer (SSP) stored in a register of the plurality of registers is selected. The register is associated with the second privilege level. By using the SSP, a shadow stack for use by the processor at the second privilege level is identified.

公开(公告)号：US11656873B2

公开(公告)日：2023-05-23

申请号：US17590648

申请日：2022-02-01

Applicant: Intel Corporation

Inventor： Vedvyas Shanbhogue ,  Gilbert Neiger ,  Deepak K. Gupta ,  H. Peter Anvin

IPC: G06F9/30 ,  G06F21/52

CPC classification number: G06F9/30134 ,  G06F9/30116 ,  G06F21/52

Abstract: An apparatus and method for efficiently managing shadow stacks. For example, one embodiment of a processor comprises: a plurality of registers to store a plurality of shadow stack pointers (SSPs); event processing circuitry to select a first SSP of the plurality of SSPs from a first register of the plurality of registers responsive to receipt of a first event associated with a first event priority level, the first SSP usable to identify a top of a first shadow stack; verification and utilization checking circuitry to determine whether the first SSP has been previously verified, wherein if the first SSP has not been previously verified then initiating a set of atomic operations to verify the first SSP and confirm that the first SSP is not in use, the set of atomic operations using a locking operation to lock data until the set of atomic operations are complete.

公开(公告)号：US11436161B2

公开(公告)日：2022-09-06

申请号：US16686379

申请日：2019-11-18

Applicant: Intel Corporation

Inventor： Ravi L. Sahita ,  Gilbert Neiger ,  Vedvyas Shanbhogue ,  David M. Durham ,  Andrew V. Anderson ,  David A. Koufaty ,  Asit K. Mallick ,  Arumugam Thiyagarajah ,  Barry E. Huntley ,  Deepak K. Gupta ,  Michael Lemay ,  Joseph F. Cihula ,  Baiju V. Patel

IPC: G06F12/00 ,  G06F12/14 ,  G06F9/455 ,  G06F12/1009 ,  G06F12/1027 ,  G06F21/78

Abstract: This disclosure is directed to a system for address mapping and translation protection. In one embodiment, processing circuitry may include a virtual machine manager (VMM) to control specific guest linear address (GLA) translations. Control may be implemented in a performance sensitive and secure manner, and may be capable of improving performance for critical linear address page walks over legacy operation by removing some or all of the cost of page walking extended page tables (EPTs) for critical mappings. Alone or in combination with the above, certain portions of a page table structure may be selectively made immutable by a VMM or early boot process using a sub-page policy (SPP). For example, SPP may enable non-volatile kernel and/or user space code and data virtual-to-physical memory mappings to be made immutable (e.g., non-writable) while allowing for modifications to non-protected portions of the OS paging structures and particularly the user space.

公开(公告)号：US11243769B2

公开(公告)日：2022-02-08

申请号：US16833599

申请日：2020-03-28

Applicant: Intel Corporation

Inventor： Vedvyas Shanbhogue ,  Gilbert Neiger ,  Deepak K. Gupta ,  H. Peter Anvin

IPC: G06F9/30 ,  G06F21/52

Abstract: An apparatus and method for efficiently managing shadow stacks. For example, one embodiment of a processor comprises: a plurality of registers to store a plurality of shadow stack pointers (SSPs), each SSP associated with a different event priority; event processing circuitry to select a first SSP of the plurality of SSPs from a first register of the plurality of registers responsive to receipt of a first event associated with a first event priority level, the first SSP usable to identify a top of a first shadow stack; verification and utilization checking circuitry to determine whether the first SSP has been previously verified, wherein if the first SSP has not been previously verified then initiating a set of atomic operations to verify the first SSP and confirm that the first SSP is not in use, the set of atomic operations using a locking operation to lock data until the set of atomic operations are complete, and wherein if the first SSP has been previously verified, then re-verifying the first SSP and confirming that the first SSP is not in use without using the locking operation.

公开(公告)号：US10394595B2

公开(公告)日：2019-08-27

申请号：US15684002

申请日：2017-08-23

Applicant: Intel Corporation

Inventor： Gilbert Neiger ,  Deepak K. Gupta ,  Ravi L. Sahita ,  Barry E. Huntley ,  Vedvyas Shanbhogue ,  Joseph F. Cihula

IPC: G06F9/455 ,  G06F12/1009 ,  G06F12/1027

Abstract: A processor comprises a register to store a first reference to a context data structure specifying a virtual machine context, the context data structure comprising a second reference to a target array and an execution unit comprising a logic circuit to execute a virtual machine (VM) based on the virtual machine context, wherein the VM comprises a guest operating system (OS) associated with a page table comprising a first memory address mapping between a guest virtual address (GVA) space and a guest physical address (GPA) space, receive a request by the guest OS to switch from the first memory address mapping to a second memory address mapping, the request comprising an index value and a first root value, retrieve an entry, identified by the index value, from the target array, the entry comprising a second root value, and responsive to determining that the first root value matches the second root value, cause a switch from the first memory address mapping to the second memory address mapping.