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    Restricting clock signal delivery in a processor
    1.
    发明授权
    Restricting clock signal delivery in a processor 有权
    限制处理器中的时钟信号传递

    公开(公告)号：US09471088B2

    公开(公告)日：2016-10-18

    申请号：US13925986

    申请日：2013-06-25

    Applicant: Intel Corporation

    Inventor： Alexander Gendler ,  Efraim Rotem ,  Julius Mandelblat ,  Alexander Lyakhov ,  Larisa Novakovsky ,  George Leifman ,  Lev Makovsky ,  Ariel Sabba ,  Niv Tokman

    IPC: G06F1/08 ,  G06F1/04 ,  G06F1/32

    CPC classification number: G06F1/08 ,  G06F1/04 ,  G06F1/32

    Abstract: In an embodiment, a processor includes a core to execute instructions, where the core includes a clock generation logic to receive and distribute a first clock signal to a plurality of units of the core, a restriction logic to receive a restriction command and to reduce delivery of the first clock signal to at least one of the plurality of units. The restriction logic may cause the first clock signal to be distributed to the plurality of units at a lower frequency than a frequency of the first clock signal. Other embodiments are described and claimed.

    Abstract translation: 在一个实施例中，处理器包括用于执行指令的核心，其中核心包括时钟生成逻辑，用于接收和分配第一时钟信号到核心的多个单元，用于接收限制命令并减少传送的限制逻辑 的第一时钟信号发送到多个单元中的至少一个。 限制逻辑可以使得第一时钟信号以比第一时钟信号的频率低的频率被分配到多个单元。 描述和要求保护其他实施例。

    Reduced power mode of a cache unit
    3.
    发明授权
    Reduced power mode of a cache unit 有权
    降低高速缓存单元的功率模式

    公开(公告)号：US09360924B2

    公开(公告)日：2016-06-07

    申请号：US13904055

    申请日：2013-05-29

    Applicant: Intel Corporation

    Inventor： Alexander Gendler ,  Larisa Novakovsky ,  Ariel Sabba ,  Niv Tokman

    IPC: G06F1/26 ,  G06F1/32 ,  G06F12/08

    CPC classification number: G06F1/3275 ,  G06F1/3206 ,  G06F12/0811 ,  G06F2201/885 ,  Y02D10/14

    Abstract: In an embodiment, a processor includes a plurality of cores and a cache unit reserved for a first core of the plurality of cores. The cache unit may include a first cache slice, a second cache slice, and power logic to switch operation of the cache unit between a first operating mode and a second operating mode. The first operating mode may include use of both the first cache slice and the second cache slice. The second operating mode may include use of the first cache slice and disabling the second cache slice. Other embodiments are described and claimed.

    Abstract translation: 在一个实施例中，处理器包括多个核心和为多个核心中的第一核心预留的高速缓存单元。 高速缓存单元可以包括第一高速缓存片，第二高速缓存片和用于在第一操作模式和第二操作模式之间切换高速缓存单元的操作的电源逻辑。 第一操作模式可以包括使用第一高速缓存片和第二高速缓存片。 第二操作模式可以包括使用第一高速缓存片并禁用第二高速缓存片。 描述和要求保护其他实施例。

    HIGH CONFIDENCE MULTIPLE BRANCH OFFSET PREDICTOR
    10.
    发明申请
    HIGH CONFIDENCE MULTIPLE BRANCH OFFSET PREDICTOR 有权

    公开(公告)号：US20220129763A1

    公开(公告)日：2022-04-28

    申请号：US17130661

    申请日：2020-12-22

    Applicant: Intel Corporation

    Inventor： Sumeet Bandishte ,  Jayesh Gaur ,  Polychronis Xekalakis ,  Ariel Sabba ,  Deborah Marr ,  Sreenivas Subramoney

    IPC: G06N5/00 ,  G06N5/04

    Abstract: An embodiment of an integrated circuit may comprise a front end unit, and circuitry coupled to the front end unit, the circuitry to provide a high confidence, multiple branch offset predictor. For example, the circuitry may be configured to identify an entry in a multiple-taken-branch prediction table that corresponds to a conditional branch instruction, determine if a confidence level of the entry exceeds a threshold confidence level, and, if so determined, provide multiple taken branch predictions that stem from the conditional branch instruction from the entry in the multiple-taken-branch prediction table. Other embodiments are disclosed and claimed.

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