公开(公告)号：US11056397B2

公开(公告)日：2021-07-06

申请号：US16635265

申请日：2017-09-26

Applicant: Intel Corporation

Inventor： Leonard P. Guler ,  Elliot Tan

IPC: H01L27/088 ,  H01L21/8234 ,  H01L29/78 ,  H01L29/66 ,  H01L21/84

Abstract: Disclosed herein are techniques for directional spacer removal, as well as related integrated circuit (IC) structures and devices. For example, in some embodiments, an IC structure may include: a first semiconductor fin having a first fin end cap; a second semiconductor fin having a second fin end cap, wherein the second fin end cap faces the first fin end cap; a first gate over the first semiconductor fin, wherein the first gate has a first gate end cap; a second gate over the second semiconductor fin, wherein the second gate has a second gate end cap facing the first gate end cap; and a gate edge isolation material adjacent to the first fin end cap, the second fin end cap, the first gate end cap, and the second gate end cap.

公开(公告)号：US20230420363A1

公开(公告)日：2023-12-28

申请号：US18314875

申请日：2023-05-10

Applicant: Intel Corporation

Inventor： Sagar Suthram ,  Elliot Tan ,  Abhishek A. Sharma ,  Shem Odhiambo Ogadhoh ,  Wilfred Gomes ,  Pushkar Sharad Ranade ,  Anand S. Murthy ,  Tahir Ghani

IPC: H01L23/528 ,  H01L27/092

CPC classification number: H01L23/528 ,  H01L27/0924

Abstract: IC devices with angled transistors and angled routing tracks, and related assemblies and methods, are disclosed herein. A transistor is referred to as an “angled transistor” if a longitudinal axis of an elongated semiconductor structure of the transistor (e.g., a fin or a nanoribbon) is neither perpendicular nor parallel to any edges of front or back sides of a support structure (e.g., a die) over which the transistor is implemented. Similarly, a routing track is referred to as an “angled routing track” if the routing track is neither perpendicular nor parallel to any edges of front or back faces of the support structure. Angled transistors and angled routing tracks provide a promising way to increasing densities of transistors on the limited real estate of semiconductor chips and/or decreasing adverse effects associated with continuous scaling of IC components.

公开(公告)号：US20200373205A1

公开(公告)日：2020-11-26

申请号：US16635265

申请日：2017-09-26

Applicant: Intel Corporation

Inventor： Leonard P. Guler ,  Elliot Tan

IPC: H01L21/8234

Abstract: Disclosed herein are techniques for directional spacer removal, as well as related integrated circuit (IC) structures and devices. For example, in some embodiments, an IC structure may include: a first semiconductor fin having a first fin end cap; a second semiconductor fin having a second fin end cap, wherein the second fin end cap faces the first fin end cap; a first gate over the first semiconductor fin, wherein the first gate has a first gate end cap; a second gate over the second semiconductor fin, wherein the second gate has a second gate end cap facing the first gate end cap; and a gate edge isolation material adjacent to the first fin end cap, the second fin end cap, the first gate end cap, and the second gate end cap.

公开(公告)号：US20240105596A1

公开(公告)日：2024-03-28

申请号：US17935627

申请日：2022-09-27

Applicant: Intel Corporation

Inventor： Abhishek A. Sharma ,  Tahir Ghani ,  Wilfred Gomes ,  Anand S. Murthy ,  Shem Ogadhoh ,  Pushkar Sharad Ranade ,  Sagar Suthram ,  Elliot Tan

IPC: H01L23/528 ,  H01L23/498

CPC classification number: H01L23/528 ,  H01L23/49838 ,  H01L24/16

Abstract: IC devices with angled interconnects are disclosed herein. An interconnect, specifically a trench or line interconnect, is referred to as an “angled interconnect” if the interconnect is neither perpendicular nor parallel to any edges of front or back faces of the support structure, or if the interconnect is not parallel or perpendicular to interconnect in another region of an interconnect layer. Angled interconnects may be used to decrease the area of pitch transition regions. Angled interconnects may also be used to decrease the area of pitch offset regions.

公开(公告)号：US11581412B2

公开(公告)日：2023-02-14

申请号：US16238428

申请日：2019-01-02

Applicant: Intel Corporation

Inventor： Elliot Tan

IPC: H01L29/423 ,  H01L29/40 ,  H01L29/78 ,  H01L21/8234 ,  H01L27/088

Abstract: Contact over active gate (COAG) structures with conductive gate taps are described. In an example, an integrated circuit structure includes a plurality of gate structures above a substrate, each of the gate structures including a gate insulating layer thereon. Each of the plurality of gate structures includes a conductive tap structure protruding through the corresponding gate insulating layer. A plurality of conductive trench contact structures is alternating with the plurality of gate structures, each of the conductive trench contact structures including a trench insulating layer thereon. An interlayer dielectric material is above the trench insulating layers and the gate insulating layers. An opening is in the interlayer dielectric material and exposes the conductive tap structure of one of the plurality of gate structures. A conductive structure is in the opening and is in direct contact with the conductive tap structure of one of the plurality of gate structures.

公开(公告)号：US11139300B2

公开(公告)日：2021-10-05

申请号：US16689789

申请日：2019-11-20

Applicant: Intel Corporation

Inventor： Wilfred Gomes ,  Mauro J. Kobrinsky ,  Abhishek A. Sharma ,  Rajesh Kumar ,  Kinyip Phoa ,  Elliot Tan ,  Tahir Ghani ,  Swaminathan Sivakumar

IPC: H01L27/108 ,  H01L27/06 ,  H01L29/786 ,  H01L23/522 ,  H01L23/528 ,  G11C5/06

Abstract: A three-dimensional memory array may include a first memory array and a second memory array, stacked above the first. Some memory cells of the first array may be coupled to a first layer selector transistor, while some memory cells of the second array may be coupled to a second layer selector transistor. The first and second layer selector transistor may be coupled to one another and to a peripheral circuit that controls operation of the first and/or second memory arrays. A different layer selector transistor may be used for each row of memory cells of a given memory array and/or for each column of memory cells of a given memory array. Such designs may allow increasing density of memory cells in a memory array having a given footprint area, or, conversely, reducing the footprint area of the memory array with a given memory cell density.

公开(公告)号：US20210151438A1

公开(公告)日：2021-05-20

申请号：US16689789

申请日：2019-11-20

Applicant: Intel Corporation

Inventor： Wilfred Gomes ,  Mauro J. Kobrinsky ,  Abhishek A. Sharma ,  Rajesh Kumar ,  Kinyip Phoa ,  Elliot Tan ,  Tahir Ghani ,  Swaminathan Sivakumar

IPC: H01L27/108 ,  G11C5/06 ,  H01L29/786 ,  H01L23/522 ,  H01L23/528 ,  H01L27/06

Abstract: A three-dimensional memory array may include a first memory array and a second memory array, stacked above the first. Some memory cells of the first array may be coupled to a first layer selector transistor, while some memory cells of the second array may be coupled to a second layer selector transistor. The first and second layer selector transistor may be coupled to one another and to a peripheral circuit that controls operation of the first and/or second memory arrays. A different layer selector transistor may be used for each row of memory cells of a given memory array and/or for each column of memory cells of a given memory array. Such designs may allow increasing density of memory cells in a memory array having a given footprint area, or, conversely, reducing the footprint area of the memory array with a given memory cell density.

公开(公告)号：US20240389300A1

公开(公告)日：2024-11-21

申请号：US18789756

申请日：2024-07-31

Applicant: Intel Corporation

Inventor： Wilfred Gomes ,  Mauro J. Kobrinsky ,  Abhishek A. Sharma ,  Rajesh Kumar ,  Kinyip Phoa ,  Elliot Tan ,  Tahir Ghani ,  Swaminathan Sivakumar

IPC: H10B12/00 ,  G11C5/06 ,  H01L23/522 ,  H01L23/528 ,  H01L27/06 ,  H01L29/786

Abstract: A three-dimensional memory array may include a first memory array and a second memory array, stacked above the first. Some memory cells of the first array may be coupled to a first layer selector transistor, while some memory cells of the second array may be coupled to a second layer selector transistor. The first and second layer selector transistor may be coupled to one another and to a peripheral circuit that controls operation of the first and/or second memory arrays. A different layer selector transistor may be used for each row of memory cells of a given memory array and/or for each column of memory cells of a given memory array. Such designs may allow increasing density of memory cells in a memory array having a given footprint area, or, conversely, reducing the footprint area of the memory array with a given memory cell density.

公开(公告)号：US20230422463A1

公开(公告)日：2023-12-28

申请号：US18312847

申请日：2023-05-05

Applicant: Intel Corporation

Inventor： Abhishek A. Sharma ,  Sagar Suthram ,  Kimberly L. Pierce ,  Elliot Tan ,  Pushkar Sharad Ranade ,  Shem Odhiambo Ogadhoh ,  Wilfred Gomes ,  Anand S. Murthy ,  Swaminathan Sivakumar ,  Tahir Ghani

IPC: H10B10/00

CPC classification number: H10B10/125

Abstract: SRAM devices with angled transistors, and related assemblies and methods, are disclosed herein. A transistor is referred to as “angled” if a longitudinal axis of an elongated semiconductor structure (e.g., a fin or a nanoribbon) based on which the transistor is built is at an angle other than 0 degrees or 90 degrees with respect to the edges of front or back faces of a support structure or a die on/in which the transistor resides, e.g., at an angle between about 10 and 80 degrees with respect to at least one of such edges. Implementing at least some of the transistors of SRAM cells as angled transistors may provide a promising way to increasing densities of SRAM cells on the limited real estate of semiconductor chips.

公开(公告)号：US20220189913A1

公开(公告)日：2022-06-16

申请号：US17117350

申请日：2020-12-10

Applicant: Intel Corporation

Inventor： Sarah Atanasov ,  Abhishek A. Sharma ,  Bernhard Sell ,  Chieh-Jen Ku ,  Elliot Tan ,  Hui Jae Yoo ,  Noriyuki Sato ,  Travis W. Lajoie ,  Van H. Le ,  Thoe Michaelos

IPC: H01L25/065 ,  H01L27/108

Abstract: Disclosed herein are transistors, memory cells, and arrangements thereof. For example, in some embodiments, an integrated circuit (IC) structure may include a plurality of transistors, wherein the transistors are distributed in a hexagonally packed arrangement. In another example, in some embodiments, an IC structure may include a memory cell including an axially symmetric transistor coupled to an axially symmetric capacitor, wherein the axis of the transistor is aligned with the axis of the capacitor.