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公开(公告)号：US20230102219A1
公开(公告)日：2023-03-30
申请号：US17478720
申请日：2021-09-17
申请人： Intel Corporation
发明人： Arnab Sen Gupta , Matthew V. Metz , Hui Jae Yoo , Justin R. Weber , Van H. Le , Jason C. Retasket , Abhishek A. Sharma , Noriyuki Sato , Yu-Jin Chen , Eric Mattson , Edward O. Johnson, JR.
IPC分类号： H01L29/45 , H01L29/786 , H01L29/78 , H01L29/66 , H01L27/108 , H01L29/417
摘要： Described herein are integrated circuit devices with metal-oxide semiconductor channels and carbon source and drain (S/D) contacts. S/D contacts conduct current to and from the semiconductor devices, e.g., to the source and drain regions of a transistor. Carbon S/D contacts may be particularly useful with semiconductor devices that use certain channel materials, such as indium gallium zinc oxide.
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公开(公告)号：US11557629B2
公开(公告)日：2023-01-17
申请号：US16367133
申请日：2019-03-27
申请人： Intel Corporation
发明人： Kaan Oguz , Christopher Wiegand , Noriyuki Sato , Angeline Smith , Tanay Gosavi
摘要： A spin orbit memory device includes a material layer stack on a spin orbit electrode. The material layer stack includes a magnetic tunnel junction (MTJ) and a synthetic antiferromagnetic (SAF) structure on the MTJ. The SAF structure includes a first magnet structure and a second magnet structure separated by an antiferromagnetic coupling layer. The first magnet structure includes a first magnet and a second magnet separated by a single layer of a non-magnetic material such as platinum. The second magnet structure includes a stack of bilayers, where each bilayer includes a layer of platinum on a layer of a magnetic material such.
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公开(公告)号：US11462678B2
公开(公告)日：2022-10-04
申请号：US16955723
申请日：2018-03-09
申请人： Intel Corporation
发明人： Kevin O'Brien , Kaan Oguz , Charles Kuo , Mark Doczy , Noriyuki Sato
摘要： A pSTTM device includes a first electrode and a second electrode, a free magnet between the first electrode and the second electrode, a fixed magnet between the first electrode and the second electrode, a tunnel barrier between the free magnet and the fixed magnet, a coupling layer between the free magnet and the first electrode, where the coupling layer comprises a metal and oxygen and a follower between the coupling layer and the first electrode, wherein the follower comprises a magnetic skyrmion. The skyrmion follower may be either magnetically and electrically coupled to the free magnet to form a coupled system of switching magnetic layers. In an embodiment, the skyrmion follower has a weaker magnetic anisotropy than an anisotropy of the free magnet.
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公开(公告)号：US11362263B2
公开(公告)日：2022-06-14
申请号：US16024411
申请日：2018-06-29
申请人： Intel Corporation
发明人： Noriyuki Sato , Tanay Gosavi , Justin Brockman , Sasikanth Manipatruni , Kaan Oguz , Kevin O'Brien , Christopher Wiegand , Angeline Smith , Tofizur Rahman , Ian Young
摘要： A perpendicular spin orbit torque (SOT) memory device includes an electrode having a spin orbit coupling material and a magnetic tunnel junction (MTJ) device on a portion of the electrode. The electrode has a first SOC layer and a second SOC layer on a portion of the first SOC layer, where at least a portion of the first SOC layer at an interface with the second SOC layer includes oxygen.
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公开(公告)号：US20220173034A1
公开(公告)日：2022-06-02
申请号：US17671543
申请日：2022-02-14
申请人： Intel Corporation
发明人： Manish Chandhok , Leonard Guler , Paul Nyhus , Gobind Bisht , Jonathan Laib , David Shykind , Gurpreet Singh , Eungnak Han , Noriyuki Sato , Charles Wallace , Jinnie Aloysius
IPC分类号： H01L23/522 , H01L23/528 , H01L21/768 , H01L29/417 , H01L29/423
摘要： An integrated circuit interconnect structure includes a first metallization level including a first metal line having a first sidewall and a second sidewall extending a length in a first direction. A second metal line is adjacent to the first metal line and a dielectric is between the first metal line and the second metal line. A second metallization level is above the first metallization level where the second metallization level includes a third metal line extending a length in a second direction orthogonal to the first direction. The third metal line extends over the first metal line and the second metal line but not beyond the first sidewall. A conductive via is between the first metal line and the third metal line where the conductive via does not extend beyond the first sidewall or beyond the second sidewall.
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公开(公告)号：US20220139823A1
公开(公告)日：2022-05-05
申请号：US17087519
申请日：2020-11-02
申请人： Intel Corporation
发明人： Kevin Lin , Noriyuki Sato , Tristan Tronic , Michael Christenson , Christopher Jezewski , Jiun-Ruey Chen , James M. Blackwell , Matthew Metz , Miriam Reshotko , Nafees Kabir , Jeffery Bielefeld , Manish Chandhok , Hui Jae Yoo , Elijah Karpov , Carl Naylor , Ramanan Chebiam
IPC分类号： H01L23/522 , H01L23/532 , H01L23/528 , H01L21/768 , H01L21/3213
摘要： IC interconnect structures including subtractively patterned features. Feature ends may be defined through multiple patterning of multiple cap materials for reduced misregistration. Subtractively patterned features may be lines integrated with damascene vias or with subtractively patterned vias, or may be vias integrated with damascene lines or with subtractively patterned lines. Subtractively patterned vias may be deposited as part of a planar metal layer and defined currently with interconnect lines. Subtractively patterned features may be integrated with air gap isolation structures. Subtractively patterned features may be include a barrier material on the bottom, top, or sidewall. A bottom barrier of a subtractively patterned features may be deposited with an area selective technique to be absent from an underlying interconnect feature. A barrier of a subtractively patterned feature may comprise graphene or a chalcogenide of a metal in the feature or in a seed layer.
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公开(公告)号：US11227644B2
公开(公告)日：2022-01-18
申请号：US15942086
申请日：2018-03-30
申请人： Intel Corporation
发明人： Kevin O'Brien , Noriyuki Sato , Kaan Oguz , Mark Doczy , Charles Kuo
摘要： A spin orbit torque (SOT) memory device includes a MTJ device on a SOT electrode, where a first portion of the SOT electrode extends beyond a sidewall of the MTJ by a first length that is no greater than a height of the MTJ, and where a second portion of the first electrode extends from the sidewall and under the MTJ by a second length that is no greater than a width of the MTJ. The MTJ device includes a free magnet, a fixed magnet and a tunnel barrier between the free magnet and the fixed magnet.
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公开(公告)号：US20210074632A1
公开(公告)日：2021-03-11
申请号：US16562346
申请日：2019-09-05
申请人： Intel Corporation
发明人： Manish Chandhok , Leonard Guler , Paul Nyhus , Gobind Bisht , Jonathan Laib , David Shykind , Gurpreet Singh , Eungnak Han , Noriyuki Sato , Charles Wallace , Jinnie Aloysius
IPC分类号： H01L23/522 , H01L23/528 , H01L21/768 , H01L29/423 , H01L29/417
摘要： An integrated circuit interconnect structure includes a first metallization level including a first metal line having a first sidewall and a second sidewall extending a length in a first direction. A second metal line is adjacent to the first metal line and a dielectric is between the first metal line and the second metal line. A second metallization level is above the first metallization level where the second metallization level includes a third metal line extending a length in a second direction orthogonal to the first direction. The third metal line extends over the first metal line and the second metal line but not beyond the first sidewall. A conductive via is between the first metal line and the third metal line where the conductive via does not extend beyond the first sidewall or beyond the second sidewall.
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公开(公告)号：US20200006630A1
公开(公告)日：2020-01-02
申请号：US16024393
申请日：2018-06-29
申请人： Intel Corporation
发明人： Noriyuki Sato , Tanay Gosavi , Gary Allen , Sasikanth Manipatruni , Kaan Oguz , Kevin O'Brien , Christopher Wiegand , Angeline Smith , Tofizur Rahman , Ian Young , Ben Buford
摘要： A spin orbit torque (SOT) memory device includes a SOT electrode having a spin orbit coupling material. The SOT electrode has a first sidewall and a second sidewall opposite to the first sidewall. The SOT memory device further includes a magnetic tunnel junction device on a portion of the SOT electrode. A first MTJ sidewall intersects the first SOT sidewall and a portion of the first MTJ sidewall and the SOT sidewall has a continuous first slope. The MTJ device has a second sidewall that does not extend beyond the second SOT sidewall and at least a portion of the second MTJ sidewall has a second slope.
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公开(公告)号：US20240304543A1
公开(公告)日：2024-09-12
申请号：US18668038
申请日：2024-05-17
申请人： Intel Corporation
发明人： Kevin Lin , Noriyuki Sato , Tristan Tronic , Michael Christenson , Christopher Jezewski , Jiun-Ruey Chen , James M. Blackwell , Matthew Metz , Miriam Reshotko , Nafees Kabir , Jeffery Bielefeld , Manish Chandhok , Hui Jae Yoo , Elijah Karpov , Carl Naylor , Ramanan Chebiam
IPC分类号： H01L23/522 , H01L21/3213 , H01L21/768 , H01L23/528 , H01L23/532
CPC分类号： H01L23/5226 , H01L21/32139 , H01L21/76819 , H01L21/7682 , H01L21/76843 , H01L23/5283 , H01L23/53209
摘要： IC interconnect structures including subtractively patterned features. Feature ends may be defined through multiple patterning of multiple cap materials for reduced misregistration. Subtractively patterned features may be lines integrated with damascene vias or with subtractively patterned vias, or may be vias integrated with damascene lines or with subtractively patterned lines. Subtractively patterned vias may be deposited as part of a planar metal layer and defined currently with interconnect lines. Subtractively patterned features may be integrated with air gap isolation structures. Subtractively patterned features may be include a barrier material on the bottom, top, or sidewall. A bottom barrier of a subtractively patterned features may be deposited with an area selective technique to be absent from an underlying interconnect feature. A barrier of a subtractively patterned feature may comprise graphene or a chalcogenide of a metal in the feature or in a seed layer.
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