公开(公告)号：US20230197728A1

公开(公告)日：2023-06-22

申请号：US17554791

申请日：2021-12-17

申请人： Intel Corporation

发明人： Nicole K. Thomas ,  Eric Mattson ,  Sudarat Lee ,  Sarah Atanasov ,  Christopher J. Jezewski ,  Charles Mokhtarzadeh ,  Thoe Michaelos ,  I-Cheng Tung ,  Charles C. Kuo ,  Scott B. Clendenning ,  Matthew V. Metz

IPC分类号： H01L27/092 ,  H01L29/06 ,  H01L29/417 ,  H01L29/78

CPC分类号： H01L27/0924 ,  H01L29/0669 ,  H01L29/41791 ,  H01L29/785 ,  H01L2029/7858

摘要： An integrated circuit includes a lower and upper device portions including bodies of semiconductor material extending horizontally between first source and drain regions in a spaced-apart vertical stack. A first gate structure is around a body in the lower device portion and includes a first gate electrode and a first gate dielectric. A second gate structure is around a body in the upper device portion and includes a second gate electrode and a second gate dielectric, where the first gate dielectric is compositionally distinct from the second gate dielectric. In some embodiments, a dipole species has a first concentration in the first gate dielectric and a different second concentration in the second gate dielectric. A method of fabrication is also disclosed.

公开(公告)号：US12046652B2

公开(公告)日：2024-07-23

申请号：US16911705

申请日：2020-06-25

申请人： Intel Corporation

发明人： Nicole Thomas ,  Michael K. Harper ,  Leonard P. Guler ,  Marko Radosavljevic ,  Thoe Michaelos

IPC分类号： H01L29/423 ,  H01L21/02 ,  H01L21/768 ,  H01L21/8234 ,  H01L29/06

CPC分类号： H01L29/42392 ,  H01L21/0228 ,  H01L21/76897 ,  H01L21/823412 ,  H01L29/0669

摘要： Embodiments disclosed herein include semiconductor devices and methods of making such devices. In an embodiment, the semiconductor device comprises a plurality of stacked semiconductor channels comprising first semiconductor channels and second semiconductor channels over the first semiconductor channels. In an embodiment a spacing is between the first semiconductor channels and the second semiconductor channels. The semiconductor device further comprises a gate dielectric surrounding individual ones of the semiconductor channels of the plurality of stacked semiconductor channels. In an embodiment, a first workfunction metal surrounds the first semiconductor channels, and a second workfunction metal surrounds the second semiconductor channels.

公开(公告)号：US20240006499A1

公开(公告)日：2024-01-04

申请号：US17854242

申请日：2022-06-30

申请人： Intel Corporation

发明人： Cheng-Ying Huang ,  Kai Loon Cheong ,  Pooja Nath ,  Susmita Ghose ,  Rambert Nahm ,  Natalie Briggs ,  Charles C. Kuo ,  Nicole K. Thomas ,  Munzarin F. Qayyum ,  Marko Radosavljevic ,  Jack T. Kavalieros ,  Thoe Michaelos ,  David Kohen

IPC分类号： H01L29/423 ,  H01L29/786 ,  H01L29/66

CPC分类号： H01L29/42392 ,  H01L29/78696 ,  H01L29/6681

摘要： An integrated circuit includes an upper semiconductor body extending in a first direction from an upper source region to an upper drain region, and a lower semiconductor body extending in the first direction from a lower source region to a lower drain region. The upper body is spaced vertically from the lower body in a second direction orthogonal to the first direction. A gate spacer structure is adjacent to the upper and lower source regions. In an example, the gate spacer structure includes (i) a first section having a first dimension in the first direction, and (ii) a second section having a second dimension in the first direction. In an example, the first dimension is different from the second dimension by at least 1 nm. In some cases, an intermediate portion of the gate spacer structure extends laterally within a given gate structure, or between upper and lower gate structures.

公开(公告)号：US20220199620A1

公开(公告)日：2022-06-23

申请号：US17127280

申请日：2020-12-18

申请人： Intel Corporation

发明人： Nicole Thomas ,  Eric Mattson ,  Sudarat Lee ,  Scott B. Clendenning ,  Tobias Brown-Heft ,  I-Cheng Tung ,  Thoe Michaelos ,  Gilbert Dewey ,  Charles Kuo ,  Matthew Metz ,  Marko Radosavljevic ,  Charles Mokhtarzadeh

IPC分类号： H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49 ,  H01L29/78 ,  H01L29/786 ,  H01L21/02 ,  H01L21/28 ,  H01L21/8238 ,  H01L29/66

摘要： Integrated circuitry comprising a ribbon or wire (RoW) transistor stack within which the transistors have different threshold voltages (Vt). In some examples, a gate electrode of the transistor stack may include only one workfunction metal. A metal oxide may be deposited around one or more channels of the transistor stack as a solid-state source of a metal oxide species that will diffuse toward the channel region(s). As diffused, the metal oxide may remain (e.g., as a silicate, or hafnate) in close proximity to the channel region, thereby altering the dipole properties of the gate insulator material. Different channels of a transistor stack may be exposed to differing amounts or types of the metal oxide species to provide a range of Vt within the stack. After diffusion, the metal oxide may be stripped as sacrificial, or retained.

公开(公告)号：US20220189913A1

公开(公告)日：2022-06-16

申请号：US17117350

申请日：2020-12-10

申请人： Intel Corporation

发明人： Sarah Atanasov ,  Abhishek A. Sharma ,  Bernhard Sell ,  Chieh-Jen Ku ,  Elliot Tan ,  Hui Jae Yoo ,  Noriyuki Sato ,  Travis W. Lajoie ,  Van H. Le ,  Thoe Michaelos

IPC分类号： H01L25/065 ,  H01L27/108

摘要： Disclosed herein are transistors, memory cells, and arrangements thereof. For example, in some embodiments, an integrated circuit (IC) structure may include a plurality of transistors, wherein the transistors are distributed in a hexagonally packed arrangement. In another example, in some embodiments, an IC structure may include a memory cell including an axially symmetric transistor coupled to an axially symmetric capacitor, wherein the axis of the transistor is aligned with the axis of the capacitor.