公开(公告)号：US20240311312A1

公开(公告)日：2024-09-19

申请号：US18121972

申请日：2023-03-15

Applicant: INTEL CORPORATION

Inventor： Jason BRANDT ,  Ido OUZIEL ,  Michael CHYNOWETH ,  Raoul RIVAS TOLEDANO ,  Gilbert NEIGER ,  Andreas KLEEN ,  Jacob DOWECK ,  Andrew NELSON

IPC: G06F12/1045

CPC classification number: G06F12/1045 ,  G06F2212/682

Abstract: An apparatus and method are described for reduced power TLB management. For example, one embodiment of a processor comprises: a plurality of cores; a first core of the plurality of cores comprising: a first translation lookaside buffer (TLB) to store address translations associated with page table walk operations, and power management logic to cause the first core to enter into a first low power state in which the address translations in the first TLB are no longer valid, wherein prior to entering into the low power state, the first core is to write an indication in a memory location that the first TLB no longer contains valid address translations; a second core of the plurality of cores to perform an operation requiring invalidation of one or more of the address translations previously stored in the first TLB, the second core to determine whether to transmit a request to the first core to invalidate the one or more address translations based on the indication.

公开(公告)号：US20210064375A1

公开(公告)日：2021-03-04

申请号：US17098129

申请日：2020-11-13

Applicant: Intel Corporation

Inventor： Gideon GERZON ,  Dror CASPI ,  Arie AHARON ,  Ido OUZIEL

IPC: G06F9/30 ,  G06F9/455 ,  G06F12/0804

Abstract: A processor includes a global register to store a value of an interrupted block count. A processor core, communicably coupled to the global register, may, upon execution of an instruction to flush blocks of a cache that are associated with a security domain: flush the blocks of the cache sequentially according to a flush loop of the cache; and in response to detection of a system interrupt: store a value of a current cache block count to the global register as the interrupted block count; and stop execution of the instruction to pause the flush of the blocks of the cache. After handling of the interrupt, the instruction may be called again to restart the flush of the cache.

公开(公告)号：US20210399882A1

公开(公告)日：2021-12-23

申请号：US17465311

申请日：2021-09-02

Applicant: Intel Corporation

Inventor： Ido OUZIEL ,  Arie AHARON ,  Dror CASPI ,  Baruch CHAIKIN ,  Jacob DOWECK ,  Gideon GERZON ,  Barry E. HUNTLEY ,  Francis X. MCKEEN ,  Gilbert NEIGER ,  Carlos V. ROZAS ,  Ravi L. SAHITA ,  Vedvyas SHANBHOGUE ,  Assaf ZALTSMAN

IPC: H04L9/08 ,  G06F9/455 ,  G06F12/1009 ,  G06F21/60 ,  G06F21/62

Abstract: A processor includes a processor core. A register of the core is to store: a bit range for a number of address bits of physical memory addresses used for key identifiers (IDs), and a first key ID to identify a boundary between non-restricted key IDs and restricted key IDs of the key identifiers. A memory controller is to: determine, via access to bit range and the first key ID in the register, a key ID range of the restricted key IDs within the physical memory addresses; access a processor state that a first logical processor of the processor core executes in an untrusted domain mode; receive a memory transaction, from the first logical processor, including an address associated with a second key ID; and generate a fault in response to a determination that the second key ID is within a key ID range of the restricted key IDs.

公开(公告)号：US20240143513A1

公开(公告)日：2024-05-02

申请号：US17958337

申请日：2022-10-01

Applicant: Intel Corporation

Inventor： Gilbert NEIGER ,  Andreas KLEEN ,  David SHEFFIELD ,  Jason BRANDT ,  Ittai ANATI ,  Vedvyas SHANBHOGUE ,  Ido OUZIEL ,  Michael S. BAIR ,  Barry E. HUNTLEY ,  Joseph NUZMAN ,  Toby OPFERMAN ,  Michael A. ROTHMAN

IPC: G06F12/1009 ,  G06F12/0811 ,  G06F12/1027

CPC classification number: G06F12/1009 ,  G06F12/0811 ,  G06F12/1027

Abstract: An apparatus and method for switching between different types of paging using separate control registers and without disabling paging. For example, one embodiment of a processor comprises: a first control register to store a first base address of a first paging structure associated with a first type of paging having a first number of paging structure levels; a second control register to store a second base address of a second paging structure associated with a first type of paging having a second number of paging structure levels greater than the first number of paging structure levels; page walk circuitry to select either the first base address from the first control register or the second base address from the second control register responsive to a first address translation request, the selection based on a characteristic of program code initiating the address translation request.