公开(公告)号：US20240311312A1

公开(公告)日：2024-09-19

申请号：US18121972

申请日：2023-03-15

Applicant: INTEL CORPORATION

Inventor： Jason BRANDT ,  Ido OUZIEL ,  Michael CHYNOWETH ,  Raoul RIVAS TOLEDANO ,  Gilbert NEIGER ,  Andreas KLEEN ,  Jacob DOWECK ,  Andrew NELSON

IPC: G06F12/1045

CPC classification number: G06F12/1045 ,  G06F2212/682

Abstract: An apparatus and method are described for reduced power TLB management. For example, one embodiment of a processor comprises: a plurality of cores; a first core of the plurality of cores comprising: a first translation lookaside buffer (TLB) to store address translations associated with page table walk operations, and power management logic to cause the first core to enter into a first low power state in which the address translations in the first TLB are no longer valid, wherein prior to entering into the low power state, the first core is to write an indication in a memory location that the first TLB no longer contains valid address translations; a second core of the plurality of cores to perform an operation requiring invalidation of one or more of the address translations previously stored in the first TLB, the second core to determine whether to transmit a request to the first core to invalidate the one or more address translations based on the indication.

公开(公告)号：US20230315453A1

公开(公告)日：2023-10-05

申请号：US17712018

申请日：2022-04-01

Applicant: Intel Corporation

Inventor： Ahmad YASIN ,  Lihu RAPPOPORT ,  Nir TELL ,  Rami BUSOOL ,  Eyal HADAS ,  Michael CHYNOWETH ,  Joseph OLIVAS ,  Christopher M. CHRULSKI

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/30058 ,  G06F9/3867

Abstract: An instruction pipeline includes a circuit that can generate a hardware event to indicate conditional branches, including the direction of taken branches. The circuit can generate a forward conditional branch indicator for an opcode when a conditional branch is taken to a forward location from the opcode. The instruction pipeline includes a counter to increment in response to the forward conditional branch indicator, which will indicate a frequency of forward conditional branches for the opcode.

公开(公告)号：US20230305742A1

公开(公告)日：2023-09-28

申请号：US18327474

申请日：2023-06-01

Applicant: Intel Corporation

Inventor： Ahmad YASIN ,  Michael CHYNOWETH ,  Rajshree CHABUKSWAR ,  Muhammad TAHER

IPC: G06F3/06 ,  G06F11/34

CPC classification number: G06F3/0656 ,  G06F3/0673 ,  G06F3/0604 ,  G06F3/0653 ,  G06F11/3466

Abstract: A processor includes a memory subunit that includes a status register and an execution engine unit to: randomly select a load operation to monitor; determine a re-order buffer identifier of the load operation; and transmit the re-order buffer identifier to the memory subsystem. Responsive to receipt of the re-order buffer identifier, the first memory subunit is to store a piece of information, related to a status of the load operation, in the status register. The processor also includes logic to, responsive to detection of retirement of the load operation, store memory information in memory-related fields of a record of a memory buffer. The memory information includes auxiliary information (AUX) and access latency information, wherein one of the auxiliary information or the access latency information includes the piece of information, from the status register, stored in a particular field of the memory-related fields.

公开(公告)号：US20200249866A1

公开(公告)日：2020-08-06

申请号：US15929272

申请日：2020-04-21

Applicant: Intel Corporation

Inventor： Ahmad YASIN ,  Michael CHYNOWETH ,  Rajshree CHABUKSWAR ,  Muhammad TAHER

IPC: G06F3/06 ,  G06F11/34

Abstract: A processor includes a memory subunit that includes a status register and an execution engine unit to: randomly select a load operation to monitor; determine a re-order buffer identifier of the load operation; and transmit the re-order buffer identifier to the memory subsystem. Responsive to receipt of the re-order buffer identifier, the first memory subunit is to store a piece of information, related to a status of the load operation, in the status register. The processor also includes logic to, responsive to detection of retirement of the load operation, store memory information in memory-related fields of a record of a memory buffer. The memory information includes auxiliary information (AUX) and access latency information, wherein one of the auxiliary information or the access latency information includes the piece of information, from the status register, stored in a particular field of the memory-related fields.