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    TECHNOLOGIES FOR DYNAMIC ACCELERATION OF GENERAL-PURPOSE CODE USING HARDWARE ACCELERATORS
    6.
    发明申请
    TECHNOLOGIES FOR DYNAMIC ACCELERATION OF GENERAL-PURPOSE CODE USING HARDWARE ACCELERATORS 审中-公开

    公开(公告)号：US20180157531A1

    公开(公告)日：2018-06-07

    申请号：US15370634

    申请日：2016-12-06

    Applicant: Intel Corporation

    Inventor： Jayaram Bobba ,  Niranjan K. Soundararajan

    IPC: G06F9/50 ,  G06F9/48

    Abstract: Technologies for dynamic acceleration of general-purpose code include a computing device having a general-purpose processor core and one or more hardware accelerators. The computing device identifies an acceleration candidate in an application that is targeted to the processor core. The acceleration candidate may be a long-running computation of the application. The computing device translates the acceleration candidate into a translated executable targeted to the hardware accelerator. The computing device determines whether to offload execution of the acceleration candidate and, if so, executes the translated executable with the hardware accelerator. The computing device may translate the acceleration candidate into multiple translated executables, each targeted to a different hardware accelerator. The computing device may select among the translated executables in response to determining to offload execution. The hardware accelerators may include, for example, a processor graphics, an image signal processor, or a field-programmable gate array. Other embodiments are described and claimed.

    INTER-ARCHITECTURE COMPATABILITY MODULE TO ALLOW CODE MODULE OF ONE ARCHITECTURE TO USE LIBRARY MODULE OF ANOTHER ARCHITECTURE
    7.
    发明申请
    INTER-ARCHITECTURE COMPATABILITY MODULE TO ALLOW CODE MODULE OF ONE ARCHITECTURE TO USE LIBRARY MODULE OF ANOTHER ARCHITECTURE 审中-公开
    允许单一架构代码模块使用其他架构的图书馆模块的架构兼容性模块

    公开(公告)号：US20150277867A1

    公开(公告)日：2015-10-01

    申请号：US14229795

    申请日：2014-03-28

    Applicant: Intel Corporation

    Inventor： Niranjan Hasabnis ,  Suresh Srinivas ,  Jayaram Bobba

    IPC: G06F9/45 ,  G06F9/445

    CPC classification number: G06F8/433 ,  G06F9/44521 ,  G06F9/4552

    Abstract: An inter-architecture compatibility apparatus of an aspect includes a control flow transfer reception module to receive a first call procedure operation, intended for a first architecture library module, from a first architecture code module. The first call procedure operation involves a first plurality of input parameters. An application binary interface (ABI) change module is coupled with the control flow transfer reception module. The ABI change module makes ABI changes to convert the first call procedure operation involving the first plurality of input parameters to a corresponding second call procedure operation involving a second plurality of input parameters. The second call procedure operation is compatible with a second architecture library module. A control flow transfer output module is coupled with the ABI change module. The control flow transfer output module provides the second call procedure operation to the second architecture library module.

    Abstract translation: 一方面的架构间兼容性装置包括控制流传输接收模块，用于从第一架构代码模块接收针对第一架构库模块的第一呼叫过程操作。 第一呼叫过程操作涉及第一多个输入参数。 应用二进制接口（ABI）更改模块与控制流传输接收模块耦合。 ABI更改模块使ABI改变，将涉及第一多个输入参数的第一呼叫过程操作转换为涉及第二多个输入参数的相应的第二呼叫过程操作。 第二个调用过程操作与第二个架构库模块兼容。 控制流传输输出模块与ABI更换模块耦合。 控制流传输输出模块向第二架构库模块提供第二呼叫过程操作。

    SYSTOLIC ARRAY ACCELERATOR SYSTEMS AND METHODS
    8.
    发明申请
    SYSTOLIC ARRAY ACCELERATOR SYSTEMS AND METHODS 审中-公开

    公开(公告)号：US20200272596A1

    公开(公告)日：2020-08-27

    申请号：US16283795

    申请日：2019-02-24

    Applicant: INTEL CORPORATION

    Inventor： Srinivasan Narayanamoorthy ,  Jayaram Bobba ,  Ankit More

    IPC: G06F15/80

    Abstract: The present disclosure is directed to systems and methods for decomposing systolic array circuitry to provide a plurality of N×N systolic sub-array circuits, apportioning a first tensor or array into a plurality of N×M first input arrays, and apportioning a second tensor or array into a plurality of M×N second input arrays. Systolic array control circuitry transfers corresponding ones of the first input arrays and second input arrays to a respective one of the plurality of N×N systolic sub-array circuits. As the elements included in the first input array and the elements included in the second input array are transferred to the systolic sub-array, the systolic sub-array performs one or more mathematical operations using the first and the second input arrays. The systems and methods beneficially improve the usage of the systolic array circuitry thereby advantageously reducing the number of clock cycles needed to perform a given number of calculations.

    Inter-architecture compatability module to allow code module of one architecture to use library module of another architecture
    10.
    发明授权
    Inter-architecture compatability module to allow code module of one architecture to use library module of another architecture 有权

    公开(公告)号：US10120663B2

    公开(公告)日：2018-11-06

    申请号：US14229795

    申请日：2014-03-28

    Applicant: Intel Corporation

    Inventor： Niranjan Hasabnis ,  Suresh Srinivas ,  Jayaram Bobba

    IPC: G06F9/44 ,  G06F9/45 ,  G06F8/41 ,  G06F9/445 ,  G06F9/455

    Abstract: An inter-architecture compatibility apparatus of an aspect includes a control flow transfer reception module to receive a first call procedure operation, intended for a first architecture library module, from a first architecture code module. The first call procedure operation involves a first plurality of input parameters. An application binary interface (ABI) change module is coupled with the control flow transfer reception module. The ABI change module makes ABI changes to convert the first call procedure operation involving the first plurality of input parameters to a corresponding second call procedure operation involving a second plurality of input parameters. The second call procedure operation is compatible with a second architecture library module. A control flow transfer output module is coupled with the ABI change module. The control flow transfer output module provides the second call procedure operation to the second architecture library module.

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