公开(公告)号：US20160070651A1

公开(公告)日：2016-03-10

申请号：US14481266

申请日：2014-09-09

Applicant: Intel Corporation

Inventor： Stanislav Shwartsman ,  Robert S. Chappell ,  Ronak Singhal ,  Ryan L. Carlson ,  Raanan Sade ,  Omar M. Shaikh ,  Liron Zur ,  Yiftach Gilad

IPC: G06F12/08

CPC classification number: G06F12/0897 ,  G06F12/0862 ,  G06F2212/1021 ,  G06F2212/402 ,  G06F2212/602

Abstract: A processor includes a cache hierarchy and an execution unit. The cache hierarchy includes a lower level cache and a higher level cache. The execution unit includes logic to issue a memory operation to access the cache hierarchy. The lower level cache includes logic to determine that a requested cache line of the memory operation is unavailable in the lower level cache, determine that a line fill buffer of the lower level cache is full, and initiate prefetching of the requested cache line from the higher level cache based upon the determination that the line fill buffer of the lower level cache is full. The line fill buffer is to forward miss requests to the higher level cache.

Abstract translation: 处理器包括缓存层级和执行单元。 高速缓存层级包括较低级别的缓存和较高级别的高速缓存。 执行单元包括发出存储器操作以访问高速缓存层级的逻辑。 下级高速缓存包括确定存储器操作的所请求的高速缓存行在下级高速缓存中不可用的逻辑，确定较低级高速缓存的行填充缓冲区已满，并且从较高级缓存启动所请求的高速缓存行的预取 基于下级缓存的行填充缓冲器的确定已满的高级缓存。 行填充缓冲区是将错误请求转发到更高级别的缓存。

公开(公告)号：US20170212825A1

公开(公告)日：2017-07-27

申请号：US15403120

申请日：2017-01-10

Applicant: Intel Corporation

Inventor： Paul Caprioli ,  Matthew C. Merten ,  Muawya M. Al-Otoom ,  Omar M. Shaikh ,  Abhay S. Kanhere ,  Suresh Srinivas ,  Koichi Yamada ,  Vivek Thakkar ,  Pawel Osciak

IPC: G06F11/34 ,  G06F9/455 ,  G06F11/36 ,  G06F11/07 ,  G06F9/45

CPC classification number: G06F11/3466 ,  G06F8/40 ,  G06F8/52 ,  G06F9/3017 ,  G06F9/3842 ,  G06F9/4552 ,  G06F11/073 ,  G06F11/3616 ,  G06F11/3652

Abstract: A hardware profiling mechanism implemented by performance monitoring hardware enables page level automatic binary translation. The hardware during runtime identifies a code page in memory containing potentially optimizable instructions. The hardware requests allocation of a new page in memory associated with the code page, where the new page contains a collection of counters and each of the counters corresponds to one of the instructions in the code page. When the hardware detects a branch instruction having a branch target within the code page, it increments one of the counters that has the same position in the new page as the branch target in the code page. The execution of the code page is repeated and the counters are incremented when branch targets fall within the code page. The hardware then provides the counter values in the new page to a binary translator for binary translation.

公开(公告)号：US10725755B2

公开(公告)日：2020-07-28

申请号：US15615798

申请日：2017-06-06

Applicant: Intel Corporation

Inventor： David J. Sager ,  Ruchira Sasanka ,  Ron Gabor ,  Shlomo Raikin ,  Joseph Nuzman ,  Leeor Peled ,  Jason A. Domer ,  Ho-Seop Kim ,  Youfeng Wu ,  Koichi Yamada ,  Tin-Fook Ngai ,  Howard H. Chen ,  Jayaram Bobba ,  Jeffrey J. Cook ,  Omar M. Shaikh ,  Suresh Srinivas

IPC: G06F8/41 ,  G06F9/38 ,  G06F9/54 ,  G06F11/36

Abstract: Systems, apparatuses, and methods for a hardware and software system to automatically decompose a program into multiple parallel threads are described. In some embodiments, the systems and apparatuses execute a method of original code decomposition and/or generated thread execution.

公开(公告)号：US09411739B2

公开(公告)日：2016-08-09

申请号：US13691218

申请日：2012-11-30

Applicant: Intel Corporation

Inventor： Omar M. Shaikh ,  Ravi Rajwar ,  Paul Caprioli ,  Muawya M. Al-Otoom

IPC: G06F12/08 ,  G06F9/46 ,  G06F9/38

CPC classification number: G06F9/3855 ,  G06F9/3004 ,  G06F9/30043 ,  G06F9/3016 ,  G06F9/3802 ,  G06F9/384 ,  G06F9/3842 ,  G06F9/3857 ,  G06F9/3863 ,  G06F9/467 ,  G06F11/1448 ,  G06F11/1469 ,  G06F12/0828 ,  G06F12/084 ,  G06F12/0842 ,  G06F12/0875 ,  G06F2201/84 ,  G06F2212/1016 ,  G06F2212/452 ,  G06F2212/507 ,  G06F2212/6042 ,  G06F2212/62 ,  G06F2212/621 ,  G06F2213/0026

Abstract: Systems, apparatuses, and methods for improving transactional memory (TM) throughput using a TM region indicator (or color) are described. Through the use of TM region indicators younger TM regions can have their instructions retired while waiting for older TM regions to commit. A copy-on-write (COW) buffer may be used to maintain a mapping from checkpointed architectural registers to physical registers, wherein the COW buffer maintains a plurality of register checkpoints for a plurality of TM regions by marking separations between TM regions using pointers, a first pointer to identify a position in the COW buffer of the last committed instruction, a retirement pointer to identify a boundary between a youngest TM region and a currently retiring position.

Abstract translation: 描述了使用TM区域指示符（或颜色）来提高事务性存储器（TM）吞吐量的系统，装置和方法。 通过使用TM区域指标，年龄较小的TM区域可以在等待旧TM区域提交时，退出指令。 可以使用写时复制（COW）缓冲器来维护从检查点架构寄存器到物理寄存器的映射，其中COW缓冲器通过使用指针标记TM区域之间的分隔来维护多个TM区域的多个寄存器检查点， 用于识别最后提交的指令的COW缓冲器中的位置的第一指针，用于识别最小TM区域和当前退休位置之间的边界的退休指针。

公开(公告)号：US09558127B2

公开(公告)日：2017-01-31

申请号：US14481266

申请日：2014-09-09

Applicant: Intel Corporation

Inventor： Stanislav Shwartsman ,  Robert S. Chappell ,  Ronak Singhal ,  Ryan L. Carlson ,  Raanan Sade ,  Omar M. Shaikh ,  Liron Zur ,  Yiftach Gilad

IPC: G06F12/08

CPC classification number: G06F12/0897 ,  G06F12/0862 ,  G06F2212/1021 ,  G06F2212/402 ,  G06F2212/602

Abstract: A processor includes a cache hierarchy and an execution unit. The cache hierarchy includes a lower level cache and a higher level cache. The execution unit includes logic to issue a memory operation to access the cache hierarchy. The lower level cache includes logic to determine that a requested cache line of the memory operation is unavailable in the lower level cache, determine that a line fill buffer of the lower level cache is full, and initiate prefetching of the requested cache line from the higher level cache based upon the determination that the line fill buffer of the lower level cache is full. The line fill buffer is to forward miss requests to the higher level cache.

Abstract translation: 处理器包括缓存层级和执行单元。 高速缓存层级包括较低级别的缓存和较高级别的高速缓存。 执行单元包括发出存储器操作以访问高速缓存层级的逻辑。 下级高速缓存包括确定存储器操作的所请求的高速缓存行在下级高速缓存中不可用的逻辑，确定较低级高速缓存的行填充缓冲区已满，并且从较高级缓存启动所请求的高速缓存行的预取 基于下级缓存的行填充缓冲器的确定已满的高级缓存。 行填充缓冲区是将错误请求转发到更高级别的缓存。

公开(公告)号：US20160350221A1

公开(公告)日：2016-12-01

申请号：US15232551

申请日：2016-08-09

Applicant: Intel Corporation

Inventor： Omar M. Shaikh ,  Ravi Rajwar ,  Paul Caprioli ,  Muawya M. Al-Otoom

IPC: G06F12/0817 ,  G06F12/0875

CPC classification number: G06F9/3855 ,  G06F9/3004 ,  G06F9/30043 ,  G06F9/3016 ,  G06F9/3802 ,  G06F9/384 ,  G06F9/3842 ,  G06F9/3857 ,  G06F9/3863 ,  G06F9/467 ,  G06F11/1448 ,  G06F11/1469 ,  G06F12/0828 ,  G06F12/084 ,  G06F12/0842 ,  G06F12/0875 ,  G06F2201/84 ,  G06F2212/1016 ,  G06F2212/452 ,  G06F2212/507 ,  G06F2212/6042 ,  G06F2212/62 ,  G06F2212/621 ,  G06F2213/0026

Abstract: Systems, apparatuses, and methods for improving TM throughput using a TM region indicator (or color) are described. Through the use of TM region indicators younger TM regions can have their instructions retired while waiting for older TM regions to commit.

Abstract translation: 描述了使用TM区域指示符（或颜色）来提高TM吞吐量的系统，装置和方法。 通过使用TM区域指标，年龄较小的TM区域可以在等待旧TM区域提交时，退出指令。