公开(公告)号：US20160294281A1

公开(公告)日：2016-10-06

申请号：US15032981

申请日：2013-12-20

Applicant: INTEL CORPORATION

Inventor： Jaydeep P. KULKARNI ,  Pascal A. MEINERZHAGEN ,  Dinesh SOMASEKHAR ,  James W. TSCHANZ ,  Vivek K. DE

IPC: H02M3/07 ,  H03K19/21 ,  G06F3/041 ,  H03K3/037

CPC classification number: H02M3/073 ,  G06F3/041 ,  H02J7/00 ,  H03K3/0377 ,  H03K19/21

Abstract: Described is an apparatus for power management. The apparatus comprises: a first power supply node; a second power supply node; a controllable device coupled to the first power supply node and to the second power supply node, the controllable device operable to short the first power supply node to the second power supply node; a load coupled to the second power supply node; and a charge recovery pump (CRP) coupled to the first and second power supply nodes.

Abstract translation: 描述了一种用于电源管理的装置。 该装置包括：第一电源节点; 第二电源节点; 耦合到所述第一电源节点和所述第二电源节点的可控设备，所述可控设备可操作以将所述第一电源节点缩短到所述第二电源节点; 耦合到所述第二电源节点的负载; 以及耦合到第一和第二电源节点的电荷恢复泵（CRP）。

公开(公告)号：US20180342289A1

公开(公告)日：2018-11-29

申请号：US15604519

申请日：2017-05-24

Applicant: Intel Corporation

Inventor： Jaydeep P. KULKARNI ,  Vivek K. De ,  Muhammad M. Khellah

IPC: G11C11/419

CPC classification number: G11C11/419

Abstract: Described is an apparatus which comprises: a memory bit-cell; a local bit-line (LBL) coupled to the memory bit-cell via a read port device; a NAND gate circuitry coupled to the LBL; and a stack of keepers coupled to the LBL, wherein at least one transistor of the stack of keepers is controllable according to an output of the NAND gate circuitry, wherein the stack of keepers includes transistors with variable strength which are to be turned on overtime.