公开(公告)号：US20200176372A1

公开(公告)日：2020-06-04

申请号：US16481421

申请日：2017-04-01

Applicant: Intel Corporation

Inventor： MD Altaf HOSSAIN ,  Dinesh SOMASEKHAR ,  Dheeraj SUBBAREDDY

IPC: H01L23/522 ,  H01L23/538 ,  H01L25/065 ,  H01L25/07 ,  H01L23/00

Abstract: Embodiments of the invention include a stacked die system and methods for forming such systems. In an embodiment, the stacked die system may include a first die. The first die may include a device layer and a plurality of routing layers formed over the device layer. The plurality of routing layers may be segmented into a plurality of sub regions. In an embodiment no conductive traces in the plurality of routing layers pass over a boundary between any of the plurality of sub regions. In an embodiment, the stacked die system may also include a plurality of second dies stacked over the first die. According to an embodiment, at least a two of the second dies are communicatively coupled to each other by a die to die interconnect formed entirely within a single sub region in the first die.

公开(公告)号：US20160294281A1

公开(公告)日：2016-10-06

申请号：US15032981

申请日：2013-12-20

Applicant: INTEL CORPORATION

Inventor： Jaydeep P. KULKARNI ,  Pascal A. MEINERZHAGEN ,  Dinesh SOMASEKHAR ,  James W. TSCHANZ ,  Vivek K. DE

IPC: H02M3/07 ,  H03K19/21 ,  G06F3/041 ,  H03K3/037

CPC classification number: H02M3/073 ,  G06F3/041 ,  H02J7/00 ,  H03K3/0377 ,  H03K19/21

Abstract: Described is an apparatus for power management. The apparatus comprises: a first power supply node; a second power supply node; a controllable device coupled to the first power supply node and to the second power supply node, the controllable device operable to short the first power supply node to the second power supply node; a load coupled to the second power supply node; and a charge recovery pump (CRP) coupled to the first and second power supply nodes.

Abstract translation: 描述了一种用于电源管理的装置。 该装置包括：第一电源节点; 第二电源节点; 耦合到所述第一电源节点和所述第二电源节点的可控设备，所述可控设备可操作以将所述第一电源节点缩短到所述第二电源节点; 耦合到所述第二电源节点的负载; 以及耦合到第一和第二电源节点的电荷恢复泵（CRP）。

公开(公告)号：US20190303159A1

公开(公告)日：2019-10-03

申请号：US15940768

申请日：2018-03-29

Applicant: Intel Corporation

Inventor： Joshua B. FRYMAN ,  Jason M. HOWARD ,  Priyanka SURESH ,  Banu Meenakshi NAGASUNDARAM ,  Srikanth DAKSHINAMOORTHY ,  Ankit MORE ,  Robert PAWLOWSKI ,  Samkit JAIN ,  Pranav YEOLEKAR ,  Avinash M. SEEGEHALLI ,  Surhud KHARE ,  Dinesh SOMASEKHAR ,  David S. DUNNING ,  Romain E. Cledat ,  William Paul GRIFFIN ,  Bhavitavya B. BHADVIYA ,  Ivan B. GANEV

IPC: G06F9/38 ,  G06F9/30

Abstract: Disclosed embodiments relate to an instruction set architecture to facilitate energy-efficient computing for exascale architectures. In one embodiment, a processor includes a plurality of accelerator cores, each having a corresponding instruction set architecture (ISA); a fetch circuit to fetch one or more instructions specifying one of the accelerator cores, a decode circuit to decode the one or more fetched instructions, and an issue circuit to translate the one or more decoded instructions into the ISA corresponding to the specified accelerator core, collate the one or more translated instructions into an instruction packet, and issue the instruction packet to the specified accelerator core; and, wherein the plurality of accelerator cores comprise a memory engine (MENG), a collective engine (CENG), a queue engine (QENG), and a chain management unit (CMU).

公开(公告)号：US20180004597A1

公开(公告)日：2018-01-04

申请号：US15197590

申请日：2016-06-29

Applicant: Intel Corporation

Inventor： Kon-Woo KWON ,  Vivek KOZHIKKOTTU ,  Dinesh SOMASEKHAR

IPC: G06F11/10 ,  G11C11/4091 ,  G06F3/06 ,  G11C29/52

CPC classification number: G11C29/52 ,  G06F11/1048 ,  G11C29/024 ,  G11C29/42

Abstract: Embodiments are generally directed to a low-overhead mechanism to detect address faults in ECC-protected memories. An embodiment of an apparatus includes a memory array; an error correction code (ECC) encoder for the memory array to encode ECC values based on a data value and a respective address value for the data value; and an ECC decoder for the memory array to decode ECC values that are based on data values and respective addresses for the data values; wherein the apparatus is to detect and correct an error in an address value based on an ECC value, address value, and data value stored in the memory.