公开(公告)号：US20200006340A1

公开(公告)日：2020-01-02

申请号：US16024064

申请日：2018-06-29

Applicant: INTEL CORPORATION

Inventor： AARON D. LILAK ,  RISHABH MEHANDRU ,  ANH PHAN ,  GILBERT DEWEY ,  WILLY RACHMADY ,  STEPHEN M. CEA ,  SAYED HASAN ,  KERRYANN M. FOLEY ,  PATRICK MORROW ,  COLIN D. LANDON ,  EHREN MANNEBACH

IPC: H01L27/092 ,  H01L27/12 ,  H01L29/78 ,  H01L29/775 ,  H01L29/423

Abstract: Stacked transistor structures and methods of forming same. In an embodiment, a stacked transistor structure has a wide central pedestal region and at least one relatively narrower channel region above and/or below the wider central pedestal region. The upper and lower channel regions are configured with a non-planar architecture, and include one or more semiconductor fins, nanowires, and/or nanoribbons. The top and bottom channel regions may be configured the same or differently, with respect to shape and/or semiconductor materials. In some cases, an outermost sidewall of one or both the top and/or bottom channel region structures, is collinear with an outermost sidewall of the wider central pedestal region. In some such cases, the outermost sidewall of the top channel region structure is collinear with the outermost sidewall of the bottom channel region structure. Top and bottom transistor structures (NMOS/PMOS) may be formed using the top and bottom channel region structures.