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    PACKET SWITCHING
    1.
    发明申请
    PACKET SWITCHING 审中-公开

    公开(公告)号：US20170339060A1

    公开(公告)日：2017-11-23

    申请号：US15613440

    申请日：2017-06-05

    Applicant: Intel Corporation

    Inventor： Mazhar I. Memon ,  Steven R. King

    IPC: H04L12/851 ,  H04L12/823 ,  H04L12/801 ,  H04L12/859 ,  H04L12/933 ,  H04L12/863

    CPC classification number: H04L47/24 ,  H04L47/10 ,  H04L47/2433 ,  H04L47/2475 ,  H04L47/2483 ,  H04L47/32 ,  H04L47/50 ,  H04L47/6255 ,  H04L47/627 ,  H04L49/109

    Abstract: In an embodiment, an apparatus is provided that may include an integrated circuit including switch circuitry to determine, at least in part, an action to be executed involving a packet. This determination may be based, at least in part, upon flow information determined, at least in part, from the packet, and packet processing policy information. The circuitry may examine the policy information to determine whether a previously-established packet processing policy has been established that corresponds, at least in part, to the flow information. If the circuitry determines, at least in part, that the policy has not been established and the packet is a first packet in a flow corresponding at least in part to the flow information, the switch circuitry may request that at least one switch control program module establish, at least in part, a new packet processing policy corresponding, at least in part, to the flow information.

    PACKET SWITCHING
    2.
    发明申请
    PACKET SWITCHING 审中-公开

    公开(公告)号：US20150195206A1

    公开(公告)日：2015-07-09

    申请号：US14563267

    申请日：2014-12-08

    Applicant: INTEL CORPORATION

    Inventor： Mazhar I. Memon ,  Steven R. King

    IPC: H04L12/851 ,  H04L12/863

    CPC classification number: H04L47/24 ,  H04L47/10 ,  H04L47/2433 ,  H04L47/2475 ,  H04L47/2483 ,  H04L47/32 ,  H04L47/50 ,  H04L47/6255 ,  H04L47/627 ,  H04L49/109

    Abstract: In an embodiment, an apparatus is provided that may include an integrated circuit including switch circuitry to determine, at least in part, an action to be executed involving a packet. This determination may be based, at least in part, upon flow information determined, at least in part, from the packet, and packet processing policy information. The circuitry may examine the policy information to determine whether a previously-established packet processing policy has been established that corresponds, at least in part, to the flow information. If the circuitry determines, at least in part, that the policy has not been established and the packet is a first packet in a flow corresponding at least in part to the flow information, the switch circuitry may request that at least one switch control program module establish, at least in part, a new packet processing policy corresponding, at least in part, to the flow information.

    Packet switching
    5.
    发明授权
    Packet switching 有权

    公开(公告)号：US09674097B2

    公开(公告)日：2017-06-06

    申请号：US14563267

    申请日：2014-12-08

    Applicant: Intel Corporation

    Inventor： Mazhar I. Memon ,  Steven R. King

    IPC: H04L12/911 ,  H04L12/851 ,  H04L12/801 ,  H04L12/823 ,  H04L12/933 ,  H04L12/859 ,  H04L12/863

    CPC classification number: H04L47/24 ,  H04L47/10 ,  H04L47/2433 ,  H04L47/2475 ,  H04L47/2483 ,  H04L47/32 ,  H04L47/50 ,  H04L47/6255 ,  H04L47/627 ,  H04L49/109

    Abstract: In an embodiment, an apparatus is provided that may include an integrated circuit including switch circuitry to determine, at least in part, an action to be executed involving a packet. This determination may be based, at least in part, upon flow information determined, at least in part, from the packet, and packet processing policy information. The circuitry may examine the policy information to determine whether a previously-established packet processing policy has been established that corresponds, at least in part, to the flow information. If the circuitry determines, at least in part, that the policy has not been established and the packet is a first packet in a flow corresponding at least in part to the flow information, the switch circuitry may request that at least one switch control program module establish, at least in part, a new packet processing policy corresponding, at least in part, to the flow information.

    Packet switching
    6.
    发明授权
    Packet switching 有权

    公开(公告)号：US10447604B2

    公开(公告)日：2019-10-15

    申请号：US15613440

    申请日：2017-06-05

    Applicant: Intel Corporation

    Inventor： Mazhar I. Memon ,  Steven R. King

    IPC: H04L12/851 ,  H04L12/801 ,  H04L12/823 ,  H04L12/933 ,  H04L12/859 ,  H04L12/863

    Abstract: In an embodiment, an apparatus is provided that may include an integrated circuit including switch circuitry to determine, at least in part, an action to be executed3 involving a packet. This determination may be based, at least in part, upon flow information determined, at least in part, from the packet, and packet processing policy information. The circuitry may examine the policy information to determine whether a previously-established packet processing policy has been established that corresponds, at least in part, to the flow information. If the circuitry determines, at least in part, that the policy has not been established and the packet is a first packet in a flow corresponding at least in part to the flow information, the switch circuitry may request that at least one switch control program module establish, at least in part, a new packet processing policy corresponding, at least in part, to the flow information.

    DATA ELEMENT SELECTION AND CONSOLIDATION PROCESSORS, METHODS, SYSTEMS, AND INSTRUCTIONS
    8.
    发明申请
    DATA ELEMENT SELECTION AND CONSOLIDATION PROCESSORS, METHODS, SYSTEMS, AND INSTRUCTIONS 审中-公开
    数据元素选择和综合处理器，方法，系统和指令

    公开(公告)号：US20160085547A1

    公开(公告)日：2016-03-24

    申请号：US14491548

    申请日：2014-09-19

    Applicant: Intel Corporation

    Inventor： Mazhar I. Memon

    IPC: G06F9/30

    CPC classification number: G06F9/30018 ,  G06F9/30032 ,  G06F9/30036

    Abstract: A processor includes packed data registers, and a decode unit to decode a data element selection and consolidation instruction. The instruction is to have a first source packed data operand that is to have a plurality of data elements, and a second source operand that is to have a plurality of mask elements. Each mask element corresponds to a different data element in the same relative position. An execution unit is coupled with the decode unit. The execution unit, in response to the instruction, is to store a result packed data operand in a destination storage location that is to be indicated by the instruction. The result packed data operand is to include all data elements of the first source packed data operand, which correspond to unmasked mask elements of the second source operand, consolidated together in a portion of the result packed data operand.

    Abstract translation: 处理器包括打包数据寄存器，以及用于解码数据元素选择和合并指令的解码单元。 该指令是具有要具有多个数据元素的第一源打包数据操作数，以及具有多个掩码元素的第二源操作数。 每个掩码元素对应于相同相对位置的不同数据元素。 执行单元与解码单元耦合。 执行单元响应于该指令，将结果打包数据操作数存储在由指令指示的目的地存储单元中。 结果打包数据操作数是将第一个源打包数据操作数的所有数据元素与第二个源操作数的未屏蔽的掩码元素相对应，合并在一起，结果打包数据操作数的一部分。

    Reducing Network Latency During Low Power Operation
    9.
    发明申请
    Reducing Network Latency During Low Power Operation 审中-公开
    在低功耗操作期间减少网络延迟

    公开(公告)号：US20150163143A1

    公开(公告)日：2015-06-11

    申请号：US14628834

    申请日：2015-02-23

    Applicant: Intel Corporation

    Inventor： Steen K. Larsen ,  Bryan E. Veal ,  Daniel S. Lake ,  Travis T. Schluessler ,  Mazhar I. Memon

    IPC: H04L12/801 ,  G06F1/32

    CPC classification number: H04L47/12 ,  G06F1/3209 ,  H04L12/12 ,  H04L49/90 ,  Y02B70/32 ,  Y02D50/40

    Abstract: In an embodiment, a method includes identifying a core of a multicore processor to which an incoming packet that is received in a packet buffer is to be directed, and if the core is powered down, transmitting a first message to cause the core to be powered up prior to arrival of the incoming packet at a head of the packet buffer. Other embodiments are described and claimed.

    Abstract translation: 在一个实施例中，一种方法包括识别多核处理器的核心，对于分组缓冲器中接收的输入分组将被引导至多核处理器，并且如果核心断电，则发送第一消息以使得核心被供电 在进入分组到达分组缓冲器的头部之前。 描述和要求保护其他实施例。

    Packet switching
    10.
    发明授权
    Packet switching 有权
    分组交换

    公开(公告)号：US08934344B2

    公开(公告)日：2015-01-13

    申请号：US14167533

    申请日：2014-01-29

    Applicant: Intel Corporation

    Inventor： Mazhar I. Memon ,  Steven R. King

    IPC: G01R31/06 ,  G06F11/00 ,  G08C15/00 ,  H04J1/16 ,  H04J3/14 ,  H04L1/00 ,  H04L12/26 ,  H04L12/863 ,  H04L12/801 ,  H04L12/851 ,  H04L12/823 ,  H04L12/933 ,  H04L12/859

    CPC classification number: H04L47/24 ,  H04L47/10 ,  H04L47/2433 ,  H04L47/2475 ,  H04L47/2483 ,  H04L47/32 ,  H04L47/50 ,  H04L47/6255 ,  H04L47/627 ,  H04L49/109

    Abstract: In an embodiment, an apparatus is provided that may include an integrated circuit including switch circuitry to determine, at least in part, an action to be executed involving a packet. This determination may be based, at least in part, upon flow information determined, at least in part, from the packet, and packet processing policy information. The circuitry may examine the policy information to determine whether a previously-established packet processing policy has been established that corresponds, at least in part, to the flow information. If the circuitry determines, at least in part, that the policy has not been established and the packet is a first packet in a flow corresponding at least in part to the flow information, the switch circuitry may request that at least one switch control program module establish, at least in part, a new packet processing policy corresponding, at least in part, to the flow information.

    Abstract translation: 在一个实施例中，提供了一种装置，其可以包括集成电路，其包括开关电路，用于至少部分地确定涉及分组的要执行的动作。 该确定可以至少部分地基于至少部分地从分组确定的流信息和分组处理策略信息。 电路可以检查策略信息以确定是否建立了至少部分地对应于流信息的先前建立的分组处理策略。 如果电路至少部分地确定策略尚未建立并且分组是至少部分地对应于流信息的流中的第一分组，则开关电路可以请求至少一个开关控制程序模块 至少部分地建立至少部分地对应于流信息的新分组处理策略。

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