公开(公告)号：US20240143513A1

公开(公告)日：2024-05-02

申请号：US17958337

申请日：2022-10-01

Applicant: Intel Corporation

Inventor： Gilbert NEIGER ,  Andreas KLEEN ,  David SHEFFIELD ,  Jason BRANDT ,  Ittai ANATI ,  Vedvyas SHANBHOGUE ,  Ido OUZIEL ,  Michael S. BAIR ,  Barry E. HUNTLEY ,  Joseph NUZMAN ,  Toby OPFERMAN ,  Michael A. ROTHMAN

IPC: G06F12/1009 ,  G06F12/0811 ,  G06F12/1027

CPC classification number: G06F12/1009 ,  G06F12/0811 ,  G06F12/1027

Abstract: An apparatus and method for switching between different types of paging using separate control registers and without disabling paging. For example, one embodiment of a processor comprises: a first control register to store a first base address of a first paging structure associated with a first type of paging having a first number of paging structure levels; a second control register to store a second base address of a second paging structure associated with a first type of paging having a second number of paging structure levels greater than the first number of paging structure levels; page walk circuitry to select either the first base address from the first control register or the second base address from the second control register responsive to a first address translation request, the selection based on a characteristic of program code initiating the address translation request.

公开(公告)号：US20200257521A1

公开(公告)日：2020-08-13

申请号：US16790488

申请日：2020-02-13

Applicant: Intel Corporation

Inventor： Sarathy JAYAKUMAR ,  Mohan J. KUMAR ,  Murugasamy K. NACHIMUTHU ,  Michael A. ROTHMAN

IPC: G06F8/656 ,  G06F9/4401 ,  G06F21/57

Abstract: Examples described herein provide a central processing unit (CPU) to reserve a region of memory for use to store both a boot firmware code and a second boot firmware code and to perform the second boot firmware code without reboot. The reserved region of memory can be a region that is not configured for access by an operating system (OS). The reserved region of memory comprises System Management Random Access Memory (SMRAM). If a first interrupt handler is not overwritten after a second boot firmware code is stored, the CPU can roll back to use of the first interrupt handler.

公开(公告)号：US20170331814A1

公开(公告)日：2017-11-16

申请号：US15585670

申请日：2017-05-03

Applicant: Intel Corporation

Inventor： Vincent J. ZIMMER ,  Michael A. ROTHMAN

IPC: H04L29/06 ,  G06F21/71 ,  G06F13/40 ,  G06F21/80 ,  G06F21/72 ,  G06F21/57 ,  H04L9/32

CPC classification number: H04L63/0823 ,  G06F13/4068 ,  G06F21/575 ,  G06F21/71 ,  G06F21/72 ,  G06F21/80 ,  G06F2221/2107 ,  G06F2221/2115 ,  H04L9/3268 ,  H04L63/0435 ,  H04L63/061 ,  H04L63/08

Abstract: In one embodiment, a method is provided that may include one or more operations. One of these operations may include, in response, at least in part, to a request to store input data in storage, encrypting, based least in part upon one or more keys, the input data to generate output data to store in the storage. The one or more keys may be authorized by a remote authority. Alternatively or additionally, another of these operations may include, in response, at least in part, to a request to retrieve the input data from the storage, decrypting, based at least in part upon the at least one key, the output data. Many modifications, variations, and alternatives are possible without departing from this embodiment

公开(公告)号：US20160246510A1

公开(公告)日：2016-08-25

申请号：US14129791

申请日：2013-10-30

Applicant: INTEL CORPORATION

Inventor： Michael A. ROTHMAN ,  Vincent J. ZIMMER ,  Daniel M. KROGH

IPC: G06F3/06 ,  G06F12/02

CPC classification number: G06F3/0607 ,  G06F3/0655 ,  G06F3/0688 ,  G06F9/44505 ,  G06F12/0246 ,  G06F21/575 ,  G06F21/79 ,  G06F2212/7202

Abstract: Technologies for providing services to a non-volatile store include a computing device having a non-volatile store policy that defines a minimum amount of reserved space in the non-volatile store. The mobile computing device receives a call for services to the non-volatile store, determines useable free space in the non-volatile store based on the non-volatile store policy, and responds to the call for services based on the useable free space. Technologies for platform configuration include a computing device having a firmware environment and an operating system. The firmware environment determines information on configuration settings inaccessible to the operating system and exports the information to the operating system. The operating system determines a new configuration setting based on the exported information, and may configure the computing device at runtime. The operating system may securely pass a configuration directive to the firmware environment for configuration during boot. Other embodiments are described and claimed.

Abstract translation: 向非易失性存储器提供服务的技术包括具有非易失性存储策略的计算设备，该非易失性存储策略定义非易失性存储器中的最小保留空间量。 移动计算设备接收对非易失性存储的服务的呼叫，基于非易失性存储策略确定非易失性存储器中的可用空闲空间，并且基于可用的可用空间来响应对服务的呼叫。 用于平台配置的技术包括具有固件环境和操作系统的计算设备。 固件环境确定关于操作系统无法访问的配置设置的信息，并将信息导出到操作系统。 操作系统基于导出的信息确定新的配置设置，并且可以在运行时配置计算设备。 操作系统可以安全地将配置指令传递给固件环境，以便在引导期间进行配置。 描述和要求保护其他实施例。

公开(公告)号：US20160188881A1

公开(公告)日：2016-06-30

申请号：US14982697

申请日：2015-12-29

Applicant: Intel Corporation

Inventor： Guo DONG ,  Jiewen YAO ,  Vincent J. ZIMMER ,  Michael A. ROTHMAN

IPC: G06F21/57 ,  G06F21/71

CPC classification number: G06F21/575 ,  G06F9/4401 ,  G06F21/71 ,  G06F2221/034 ,  G09C1/00 ,  H04L2209/127

Abstract: Technologies for improving platform initialization on a computing device include beginning initialization of a platform of the computing device using a basic input/output system (BIOS) of the computing device. A security co-processor driver module adds a security co-processor command to a command list when a security processor command is received from the BIOS module. The computing device establishes a periodic interrupt of the initialization of the platform to query the security co-processor regarding the availability of a response to a previously submitted security co-processor command, forward any responses received by the security co-processor driver module to the BIOS module, and submit the next security co-processor command in the command list to the security co-processor.