公开(公告)号：US20180190604A1

公开(公告)日：2018-07-05

申请号：US15394460

申请日：2016-12-29

Applicant: INTEL CORPORATION

Inventor： Mihir A. OKA ,  Ken P. HACKENBERG ,  Vijay Krishnan (Vijay) SUBRAMANIAN ,  Neha M. PATEL ,  Nachiket R. RARAVIKAR

IPC: H01L23/00

CPC classification number: H01L24/05 ,  H01L24/03 ,  H01L24/19 ,  H01L24/20 ,  H01L2224/02311 ,  H01L2224/02371 ,  H01L2224/0401 ,  H01L2224/13024 ,  H01L2224/13025 ,  H01L2224/211 ,  H01L2924/014 ,  H01L2924/3841

Abstract: Foundation layers and methods of forming a foundation layer are described. Die pads are formed over a die. A dielectric layer is formed over die pads and the die. The dielectric layer is then recessed to expose top portions of the die pads. A first plurality of sintered conductive vias are formed over the die pads. The first sintered conductive vias are coupled to at least one of the die pads. In addition, a photoresist layer may be formed over the dielectric layer and the top portions of the die pads. Via openings are formed in the photoresist layer. A second plurality of sintered conductive vias may then be formed over the first sintered conductive vias to form a plurality of sintered conductive lines. Each of the first and second sintered conductive vias are formed with a liquid phase sintering (LPS) solder paste.

公开(公告)号：US20190157225A1

公开(公告)日：2019-05-23

申请号：US16260908

申请日：2019-01-29

Applicant: Intel Corporation

Inventor： Mihir A. OKA ,  Ken P. HACKENBERG ,  Vijay Krishnan (Vijay) SUBRAMANIAN ,  Neha M. PATEL ,  Nachiket R. RARAVIKAR

IPC: H01L23/00

Abstract: Foundation layers and methods of forming a foundation layer are described. Die pads are formed over a die. A dielectric layer is formed over die pads and the die. The dielectric layer is then recessed to expose top portions of the die pads. A first plurality of sintered conductive vias are formed over the die pads. The first sintered conductive vias are coupled to at least one of the die pads. In addition, a photoresist layer may be formed over the dielectric layer and the top portions of the die pads. Via openings are formed in the photoresist layer. A second plurality of sintered conductive vias may then be formed over the first sintered conductive vias to form a plurality of sintered conductive lines. Each of the first and second sintered conductive vias are formed with a liquid phase sintering (LPS) solder paste.